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The generic irqentry code now provides irqentry_exit_to_kernel_mode_preempt() and irqentry_exit_to_kernel_mode_after_preempt(), which can be used where architectures have different state requirements for involuntary preemption and exception return, as is the case on arm64. Use the new functions on arm64, aligning our exit to kernel mode logic with the style of our exit to user mode logic. This removes the need for the recently-added bodge in arch_irqentry_exit_need_resched(), and allows preemption to occur when returning from any exception taken from kernel mode, which is nicer for RT. In an ideal world, we'd remove arch_irqentry_exit_need_resched(), and fold the conditionality directly into the architecture-specific entry code. That way all the logic necessary to avoid preempting from a pseudo-NMI could be constrained specifically to the EL1 IRQ/FIQ paths, avoiding redundant work for other exceptions, and making the flow a bit clearer. At present it looks like that would require a larger refactoring (e.g. for the PREEMPT_DYNAMIC logic), and so I've left that as-is for now. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Jinjie Ruan <ruanjinjie@huawei.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@kernel.org> Cc: Vladimir Murzin <vladimir.murzin@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARM64_ENTRY_COMMON_H
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#define _ASM_ARM64_ENTRY_COMMON_H
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#include <linux/thread_info.h>
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#include <asm/cpufeature.h>
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#include <asm/daifflags.h>
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#include <asm/fpsimd.h>
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#include <asm/mte.h>
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#include <asm/stacktrace.h>
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#define ARCH_EXIT_TO_USER_MODE_WORK (_TIF_MTE_ASYNC_FAULT | _TIF_FOREIGN_FPSTATE)
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static __always_inline void arch_exit_to_user_mode_work(struct pt_regs *regs,
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unsigned long ti_work)
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{
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if (ti_work & _TIF_MTE_ASYNC_FAULT) {
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clear_thread_flag(TIF_MTE_ASYNC_FAULT);
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send_sig_fault(SIGSEGV, SEGV_MTEAERR, (void __user *)NULL, current);
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}
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if (ti_work & _TIF_FOREIGN_FPSTATE)
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fpsimd_restore_current_state();
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}
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#define arch_exit_to_user_mode_work arch_exit_to_user_mode_work
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static inline bool arch_irqentry_exit_need_resched(void)
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{
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/*
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* DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
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* priority masking is used the GIC irqchip driver will clear DAIF.IF
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* using gic_arch_enable_irqs() for normal IRQs. If anything is set in
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* DAIF we must have handled an NMI, so skip preemption.
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*/
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if (system_uses_irq_prio_masking() && read_sysreg(daif))
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return false;
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/*
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* Preempting a task from an IRQ means we leave copies of PSTATE
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* on the stack. cpufeature's enable calls may modify PSTATE, but
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* resuming one of these preempted tasks would undo those changes.
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*
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* Only allow a task to be preempted once cpufeatures have been
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* enabled.
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*/
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if (!system_capabilities_finalized())
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return false;
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return true;
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}
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#define arch_irqentry_exit_need_resched arch_irqentry_exit_need_resched
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#endif /* _ASM_ARM64_ENTRY_COMMON_H */
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