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5d5b43f59b
If the hardware supports extended tag field (8-bit ones), then enable it.
This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).
In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.
Fixes: fdo#86537
v2: Restrict changes to chipsets >= 0x84
v3:
* Add nvkm_pci_mask to pci.h
* Mask bit 8 before setting it
v4:
* Rename `add` argument of nvkm_pci_mask to `value`
* Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
checks
v5:
* Rebase code on latest PCI structure
* Restore PCIe check
* Fix namings in nvkm_pci_mask
* Rephrase part of the commit message
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
26 lines
779 B
C
26 lines
779 B
C
#ifndef __NVKM_PCI_PRIV_H__
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#define __NVKM_PCI_PRIV_H__
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#define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev)
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#include <subdev/pci.h>
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int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *,
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int index, struct nvkm_pci **);
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struct nvkm_pci_func {
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void (*init)(struct nvkm_pci *);
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u32 (*rd32)(struct nvkm_pci *, u16 addr);
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void (*wr08)(struct nvkm_pci *, u16 addr, u8 data);
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void (*wr32)(struct nvkm_pci *, u16 addr, u32 data);
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void (*msi_rearm)(struct nvkm_pci *);
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};
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u32 nv40_pci_rd32(struct nvkm_pci *, u16);
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void nv40_pci_wr08(struct nvkm_pci *, u16, u8);
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void nv40_pci_wr32(struct nvkm_pci *, u16, u32);
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void nv40_pci_msi_rearm(struct nvkm_pci *);
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void nv46_pci_msi_rearm(struct nvkm_pci *);
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void g84_pci_init(struct nvkm_pci *pci);
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#endif
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