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core/region.c is overloaded with per-region control logic (pmem, dax, sysram, etc). Move the CXL DAX region device infrastructure from region.c into a new region_dax.c file. This will also allow us to add additional dax-driver integration paths that don't further dirty the core region.c logic. No functional changes. Signed-off-by: Gregory Price <gourry@gourry.net> Co-developed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260327020203.876122-3-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
25 lines
739 B
Makefile
25 lines
739 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CXL_BUS) += cxl_core.o
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obj-$(CONFIG_CXL_SUSPEND) += suspend.o
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ccflags-y += -I$(srctree)/drivers/cxl
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CFLAGS_trace.o = -DTRACE_INCLUDE_PATH=. -I$(src)
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cxl_core-y := port.o
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cxl_core-y += pmem.o
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cxl_core-y += regs.o
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cxl_core-y += memdev.o
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cxl_core-y += mbox.o
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cxl_core-y += pci.o
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cxl_core-y += hdm.o
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cxl_core-y += pmu.o
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cxl_core-y += cdat.o
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cxl_core-$(CONFIG_TRACING) += trace.o
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cxl_core-$(CONFIG_CXL_REGION) += region.o region_pmem.o region_dax.o
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cxl_core-$(CONFIG_CXL_MCE) += mce.o
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cxl_core-$(CONFIG_CXL_FEATURES) += features.o
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cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += edac.o
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cxl_core-$(CONFIG_CXL_RAS) += ras.o
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cxl_core-$(CONFIG_CXL_RAS) += ras_rch.o
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cxl_core-$(CONFIG_CXL_ATL) += atl.o
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