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The current probe time ownership check for Soft Reserved memory based solely on CXL window intersection is insufficient. dax_hmem probing is not always guaranteed to run after CXL enumeration and region assembly, which can lead to incorrect ownership decisions before the CXL stack has finished publishing windows and assembling committed regions. Introduce deferred ownership handling for Soft Reserved ranges that intersect CXL windows. When such a range is encountered during the initial dax_hmem probe, schedule deferred work to wait for the CXL stack to complete enumeration and region assembly before deciding ownership. Once the deferred work runs, evaluate each Soft Reserved range individually: if a CXL region fully contains the range, skip it and let dax_cxl bind. Otherwise, register it with dax_hmem. This per-range ownership model avoids the need for CXL region teardown and alloc_dax_region() resource exclusion prevents double claiming. Introduce a boolean flag dax_hmem_initial_probe to live inside device.c so it survives module reload. Ensure dax_cxl defers driver registration until dax_hmem has completed ownership resolution. dax_cxl calls dax_hmem_flush_work() before cxl_driver_register(), which both waits for the deferred work to complete and creates a module symbol dependency that forces dax_hmem.ko to load before dax_cxl. Co-developed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260322195343.206900-9-Smita.KoralahalliChannabasappa@amd.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
76 lines
1.9 KiB
C
76 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2023 Intel Corporation. All rights reserved. */
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#include <linux/module.h>
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#include <linux/dax.h>
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#include "../cxl/cxl.h"
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#include "bus.h"
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static int cxl_dax_region_probe(struct device *dev)
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{
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struct cxl_dax_region *cxlr_dax = to_cxl_dax_region(dev);
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int nid = phys_to_target_node(cxlr_dax->hpa_range.start);
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struct cxl_region *cxlr = cxlr_dax->cxlr;
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struct dax_region *dax_region;
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struct dev_dax_data data;
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if (nid == NUMA_NO_NODE)
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nid = memory_add_physaddr_to_nid(cxlr_dax->hpa_range.start);
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dax_region = alloc_dax_region(dev, cxlr->id, &cxlr_dax->hpa_range, nid,
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PMD_SIZE, IORESOURCE_DAX_KMEM);
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if (!dax_region)
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return -ENOMEM;
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data = (struct dev_dax_data) {
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.dax_region = dax_region,
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.id = -1,
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.size = range_len(&cxlr_dax->hpa_range),
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.memmap_on_memory = true,
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};
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return PTR_ERR_OR_ZERO(devm_create_dev_dax(&data));
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}
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static struct cxl_driver cxl_dax_region_driver = {
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.name = "cxl_dax_region",
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.probe = cxl_dax_region_probe,
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.id = CXL_DEVICE_DAX_REGION,
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.drv = {
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.suppress_bind_attrs = true,
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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},
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};
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static void cxl_dax_region_driver_register(struct work_struct *work)
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{
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dax_hmem_flush_work();
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cxl_driver_register(&cxl_dax_region_driver);
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}
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static DECLARE_WORK(cxl_dax_region_driver_work, cxl_dax_region_driver_register);
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static int __init cxl_dax_region_init(void)
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{
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/*
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* Need to resolve a race with dax_hmem wanting to drive regions
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* instead of CXL
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*/
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queue_work(system_long_wq, &cxl_dax_region_driver_work);
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return 0;
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}
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module_init(cxl_dax_region_init);
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static void __exit cxl_dax_region_exit(void)
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{
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flush_work(&cxl_dax_region_driver_work);
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cxl_driver_unregister(&cxl_dax_region_driver);
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}
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module_exit(cxl_dax_region_exit);
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MODULE_ALIAS_CXL(CXL_DEVICE_DAX_REGION);
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MODULE_DESCRIPTION("CXL DAX: direct access to CXL regions");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_IMPORT_NS("CXL");
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