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Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how the 14 IRQs are wired to the platform's internal interrupt controller by devicetree. Signed-off-by: Liu Peibao <liupeibao@loongson.cn> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221114113824.1880-3-liupeibao@loongson.cn
35 lines
726 B
YAML
35 lines
726 B
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LoongArch CPU Interrupt Controller
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maintainers:
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- Liu Peibao <liupeibao@loongson.cn>
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properties:
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compatible:
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const: loongarch,cpu-interrupt-controller
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'#interrupt-cells':
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const: 1
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interrupt-controller: true
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additionalProperties: false
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required:
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- compatible
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- '#interrupt-cells'
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- interrupt-controller
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examples:
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- |
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interrupt-controller {
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compatible = "loongarch,cpu-interrupt-controller";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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