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0eaa8d1c36
Move MSM8996 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. - Expecting eight MSI interrupts and one global, instead of only one, which was incomplete hardware description. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-11-873721599754@oss.qualcomm.com
157 lines
4.2 KiB
YAML
157 lines
4.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-msm8996.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm MSM8996 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,pcie-msm8996
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- items:
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- const: qcom,pcie-msm8998
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- const: qcom,pcie-msm8996
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: config
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- const: mhi
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clocks:
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maxItems: 5
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clock-names:
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items:
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- const: pipe # Pipe Clock driving internal logic
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- const: aux
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- const: cfg
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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interrupts:
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minItems: 8
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maxItems: 9
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interrupt-names:
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minItems: 8
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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vdda-supply:
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description: A phandle to the core analog power supply
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vddpe-3v3-supply:
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description: A phandle to the PCIe endpoint power supply
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required:
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- power-domains
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@600000 {
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compatible = "qcom,pcie-msm8996";
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reg = <0x00600000 0x2000>,
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<0x0c000000 0xf1d>,
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<0x0c000f20 0xa8>,
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<0x0c100000 0x100000>;
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reg-names = "parf", "dbi", "elbi", "config";
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ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
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<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
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device_type = "pci";
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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linux,pci-domain = <0>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
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clock-names = "pipe",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave";
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interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_state_on>;
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pinctrl-1 = <&pcie0_state_off>;
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phys = <&pciephy_0>;
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phy-names = "pciephy";
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power-domains = <&gcc PCIE0_GDSC>;
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perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
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vddpe-3v3-supply = <&wlan_en>;
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vdda-supply = <&vreg_l28a_0p925>;
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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