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c86e1f39f6
Move SDX55 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. - Adding interrupts based on the DTS, which were missing in the all-in-one binding. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-2-873721599754@oss.qualcomm.com
173 lines
4.5 KiB
YAML
173 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDX55 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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enum:
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- qcom,pcie-sdx55
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: atu
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- const: config
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- const: mhi
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clocks:
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maxItems: 7
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clock-names:
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items:
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- const: pipe
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- const: aux
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- const: cfg
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a
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- const: sleep
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interrupts:
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maxItems: 8
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interrupt-names:
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items:
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- const: msi
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: msi8
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci
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required:
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- power-domains
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- resets
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- reset-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@1c00000 {
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compatible = "qcom,pcie-sdx55";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xc8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config";
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ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"msi8";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>;
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clock-names = "pipe",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"sleep";
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assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
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<0x100 &apps_smmu 0x0201 0x1>,
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<0x200 &apps_smmu 0x0202 0x1>,
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<0x300 &apps_smmu 0x0203 0x1>,
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<0x400 &apps_smmu 0x0204 0x1>;
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power-domains = <&gcc PCIE_GDSC>;
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phys = <&pcie_phy>;
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phy-names = "pciephy";
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resets = <&gcc GCC_PCIE_BCR>;
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reset-names = "pci";
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perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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