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9ec280529a
Most of the per-chipset differences will go away when we fully switch to using the register lists provided by the firmware files, which will leave all the remaining code "belonging" to GM200. This is a preemptive rename from GM204 to GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
104 lines
3.1 KiB
C
104 lines
3.1 KiB
C
/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "ctxgf100.h"
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static void
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gm20b_grctx_generate_r406028(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 tpc_per_gpc = 0;
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int i;
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for (i = 0; i < gr->gpc_nr; i++)
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tpc_per_gpc |= gr->tpc_nr[i] << (4 * i);
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nvkm_wr32(device, 0x406028, tpc_per_gpc);
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nvkm_wr32(device, 0x405870, tpc_per_gpc);
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}
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static void
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gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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int idle_timeout_save;
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int i, tmp;
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gf100_gr_mmio(gr, gr->fuc_sw_ctx);
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gf100_gr_wait_idle(gr);
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idle_timeout_save = nvkm_rd32(device, 0x404154);
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nvkm_wr32(device, 0x404154, 0x00000000);
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grctx->attrib(info);
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grctx->unkn(gr);
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gm200_grctx_generate_tpcid(gr);
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gm20b_grctx_generate_r406028(gr);
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gk104_grctx_generate_r418bb8(gr);
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for (i = 0; i < 8; i++)
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nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
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nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
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gk104_grctx_generate_rop_active_fbps(gr);
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nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
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for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
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tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
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nvkm_wr32(device, 0x4041c4, tmp);
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gm200_grctx_generate_405b60(gr);
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gf100_gr_wait_idle(gr);
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nvkm_wr32(device, 0x404154, idle_timeout_save);
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gf100_gr_wait_idle(gr);
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gf100_gr_mthd(gr, gr->fuc_method);
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gf100_gr_wait_idle(gr);
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gf100_gr_icmd(gr, gr->fuc_bundle);
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grctx->pagepool(info);
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grctx->bundle(info);
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}
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const struct gf100_grctx_func
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gm20b_grctx = {
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.main = gm20b_grctx_generate_main,
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.unkn = gk104_grctx_generate_unkn,
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.bundle = gm107_grctx_generate_bundle,
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.bundle_size = 0x1800,
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.bundle_min_gpm_fifo_depth = 0x182,
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.bundle_token_limit = 0x1c0,
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.pagepool = gm107_grctx_generate_pagepool,
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.pagepool_size = 0x8000,
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.attrib = gm107_grctx_generate_attrib,
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.attrib_nr_max = 0x600,
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.attrib_nr = 0x400,
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.alpha_nr_max = 0xc00,
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.alpha_nr = 0x800,
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};
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