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923f1bd27b
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
86 lines
2.7 KiB
C
86 lines
2.7 KiB
C
/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <subdev/timer.h>
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#include <nvif/class.h>
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static void
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gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 val;
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/* Bypass MMU check for non-secure boot */
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if (!device->secboot) {
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nvkm_wr32(device, 0x100ce4, 0xffffffff);
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if (nvkm_rd32(device, 0x100ce4) != 0xffffffff)
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nvdev_warn(device,
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"cannot bypass secure boot - expect failure soon!\n");
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}
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val = nvkm_rd32(device, 0x100c80);
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val &= 0xf000087f;
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nvkm_wr32(device, 0x418880, val);
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nvkm_wr32(device, 0x418890, 0);
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nvkm_wr32(device, 0x418894, 0);
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nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
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nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
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nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
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nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));
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}
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static void
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gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x419e44, 0xdffffe);
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nvkm_wr32(device, 0x419e4c, 0x5);
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}
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static const struct gf100_gr_func
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gm20b_gr = {
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.init = gk20a_gr_init,
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.init_gpc_mmu = gm20b_gr_init_gpc_mmu,
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.set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
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.ppc_nr = 1,
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.grctx = &gm20b_grctx,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, MAXWELL_B, &gf100_fermi },
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{ -1, -1, MAXWELL_COMPUTE_B },
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{}
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}
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};
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int
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gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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{
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return gm200_gr_new_(&gm20b_gr, device, index, pgr);
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}
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