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The Page Request Interface (PRI) is an optional PCIe feature. As such, a SMMU would not need to handle it if the PCIe host bridge or the SMMU itself do not implement it. Also an SMMU could be connected to a platform device, without any PRI functionality whatsoever. In all cases there would be no SMMU PRI queue interrupt to be wired up to an interrupt controller. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we would need to sacrifice the command queue sync interrupt as well, which might not be desired. Relax the binding to allow specifying certain useful combinations of wired interrupts, for instance just the "gerror" interrupt, or omitting both "pri" and "cmdq-sync". Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220506140533.3566431-2-andre.przywara@arm.com
101 lines
2.8 KiB
YAML
101 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM SMMUv3 Architecture Implementation
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maintainers:
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- Will Deacon <will@kernel.org>
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- Robin Murphy <Robin.Murphy@arm.com>
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description: |+
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The SMMUv3 architecture is a significant departure from previous
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revisions, replacing the MMIO register interface with in-memory command
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and event queues and adding support for the ATS and PRI components of
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the PCIe specification.
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properties:
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$nodename:
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pattern: "^iommu@[0-9a-f]*"
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compatible:
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const: arm,smmu-v3
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 4
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interrupt-names:
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oneOf:
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- const: combined
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description:
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The combined interrupt is optional, and should only be provided if the
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hardware supports just a single, combined interrupt line.
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If provided, then the combined interrupt will be used in preference to
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any others.
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- minItems: 1
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items:
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- enum:
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- eventq # Event Queue not empty
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- gerror # Global Error activated
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- const: gerror
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- enum:
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- cmdq-sync # CMD_SYNC complete
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- priq # PRI Queue not empty
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- enum:
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- cmdq-sync
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- priq
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'#iommu-cells':
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const: 1
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dma-coherent:
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description: |
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Present if page table walks made by the SMMU are cache coherent with the
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CPU.
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NOTE: this only applies to the SMMU itself, not masters connected
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upstream of the SMMU.
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msi-parent: true
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hisilicon,broken-prefetch-cmd:
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type: boolean
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description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
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cavium,cn9900-broken-page1-regspace:
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type: boolean
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description:
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Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
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register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
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doesn't support SMMU page1 register space.
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required:
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- compatible
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- reg
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- '#iommu-cells'
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additionalProperties: false
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examples:
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- |+
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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iommu@2b400000 {
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compatible = "arm,smmu-v3";
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reg = <0x2b400000 0x20000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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dma-coherent;
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#iommu-cells = <1>;
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msi-parent = <&its 0xff0000>;
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};
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