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cdeffe87f7
Pull mailbox updates from Jassi Brar: "api: - hrtimer fix qcom: - log pending irq during resume - minor cosmetic changes omap: - use pm_runtime_resume_and_get imx: - use pm_runtime_resume_and_get - remove redundant initializer mtk: - added GCE header for MT8186 - enable support for MT8186 tegra: - remove redundant NULL check - added hsp_sm_ops for send/recv api - support shared mailboxes stm: - remove unsupported "wakeup" irq pcc: - sanitize mbox allocated memory before use misc: - documentation fixes for arm_mhu and qcom-ipcc" * tag 'mailbox-v5.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: qcom-ipcc: Fix -Wunused-function with CONFIG_PM_SLEEP=n mailbox: forward the hrtimer if not queued and under a lock mailbox: qcom-ipcc: Log the pending interrupt during resume mailbox: pcc: Fix an invalid-load caught by the address sanitizer dt-bindings: mailbox: remove the IPCC "wakeup" IRQ mailbox: correct kerneldoc mailbox: omap: using pm_runtime_resume_and_get to simplify the code mailbox:imx: using pm_runtime_resume_and_get mailbox: mediatek: support mt8186 adsp mailbox dt-bindings: mailbox: mtk,adsp-mbox: add mt8186 compatible name mailbox: tegra-hsp: Add 128-bit shared mailbox support dt-bindings: tegra186-hsp: add type for shared mailboxes mailbox: tegra-hsp: Add tegra_hsp_sm_ops dt-bindings: gce: add the GCE header file for MT8186 mailbox: remove an unneeded NULL check on list iterator mailbox: imx: remove redundant initializer dt-bindings: mailbox: qcom-ipcc: simplify the example
76 lines
2.1 KiB
YAML
76 lines
2.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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The Inter-Processor Communication Controller (IPCC) is a centralized hardware
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to route interrupts across various subsystems. It involves a three-level
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addressing scheme called protocol, client and signal. For example, consider an
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entity on the Application Processor Subsystem (APSS) that wants to listen to
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Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
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a case, the client would be Modem (client-id is 2) and the signal would be
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SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
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protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
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for the list of such IDs.
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properties:
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compatible:
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items:
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- enum:
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- qcom,sm6350-ipcc
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- qcom,sm8250-ipcc
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- qcom,sm8350-ipcc
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- qcom,sm8450-ipcc
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- qcom,sc7280-ipcc
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- const: qcom,ipcc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 3
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description:
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The first cell is the client-id, the second cell is the signal-id and the
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third cell is the interrupt type.
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"#mbox-cells":
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const: 2
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description:
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The first cell is the client-id, and the second cell is the signal-id.
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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mailbox@408000 {
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compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
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reg = <0x408000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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