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4e71ed9853
Now that the schema tools can extract type information for all properties (in order to decode dtb files), finding properties missing any type definition is fairly trivial though not yet automated. Fix the various property schemas which are missing a type. Most of these tend to be device specific properties which don't have a vendor prefix. A vendor prefix is how we normally ensure a type is defined. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> # for everything in .../bindings/display/ Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220519211411.2200720-1-robh@kernel.org
162 lines
4.4 KiB
YAML
162 lines
4.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Core Power Reduction (CPR) bindings
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maintainers:
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- Niklas Cassel <nks@flawful.org>
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description: |
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CPR (Core Power Reduction) is a technology to reduce core power on a CPU
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or other device. Each OPP of a device corresponds to a "corner" that has
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a range of valid voltages for a particular frequency. While the device is
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running at a particular frequency, CPR monitors dynamic factors such as
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temperature, etc. and suggests adjustments to the voltage to save power
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and meet silicon characteristic requirements.
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properties:
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compatible:
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items:
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- enum:
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- qcom,qcs404-cpr
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- const: qcom,cpr
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reg:
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description: Base address and size of the RBCPR register region.
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Reference clock.
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clock-names:
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items:
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- const: ref
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vdd-apc-supply:
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description: APC regulator supply.
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'#power-domain-cells':
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const: 0
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operating-points-v2:
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description: |
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A phandle to the OPP table containing the performance states
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supported by the CPR power domain.
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acc-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to the syscon used for writing ACC settings.
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nvmem-cells:
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items:
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- description: Corner 1 quotient offset
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- description: Corner 2 quotient offset
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- description: Corner 3 quotient offset
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- description: Corner 1 initial voltage
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- description: Corner 2 initial voltage
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- description: Corner 3 initial voltage
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- description: Corner 1 quotient
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- description: Corner 2 quotient
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- description: Corner 3 quotient
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- description: Corner 1 ring oscillator
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- description: Corner 2 ring oscillator
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- description: Corner 3 ring oscillator
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- description: Fuse revision
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nvmem-cell-names:
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items:
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- const: cpr_quotient_offset1
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- const: cpr_quotient_offset2
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- const: cpr_quotient_offset3
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- const: cpr_init_voltage1
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- const: cpr_init_voltage2
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- const: cpr_init_voltage3
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- const: cpr_quotient1
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- const: cpr_quotient2
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- const: cpr_quotient3
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- const: cpr_ring_osc1
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- const: cpr_ring_osc2
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- const: cpr_ring_osc3
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- const: cpr_fuse_revision
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- vdd-apc-supply
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- '#power-domain-cells'
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- operating-points-v2
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- nvmem-cells
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- nvmem-cell-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cpr_opp_table: opp-table-cpr {
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compatible = "operating-points-v2-qcom-level";
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cpr_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cpr_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cpr_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <3>;
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};
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};
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power-controller@b018000 {
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compatible = "qcom,qcs404-cpr", "qcom,cpr";
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reg = <0x0b018000 0x1000>;
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interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xo_board>;
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clock-names = "ref";
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vdd-apc-supply = <&pms405_s3>;
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#power-domain-cells = <0>;
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operating-points-v2 = <&cpr_opp_table>;
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acc-syscon = <&tcsr>;
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nvmem-cells = <&cpr_efuse_quot_offset1>,
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<&cpr_efuse_quot_offset2>,
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<&cpr_efuse_quot_offset3>,
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<&cpr_efuse_init_voltage1>,
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<&cpr_efuse_init_voltage2>,
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<&cpr_efuse_init_voltage3>,
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<&cpr_efuse_quot1>,
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<&cpr_efuse_quot2>,
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<&cpr_efuse_quot3>,
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<&cpr_efuse_ring1>,
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<&cpr_efuse_ring2>,
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<&cpr_efuse_ring3>,
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<&cpr_efuse_revision>;
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nvmem-cell-names = "cpr_quotient_offset1",
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"cpr_quotient_offset2",
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"cpr_quotient_offset3",
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"cpr_init_voltage1",
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"cpr_init_voltage2",
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"cpr_init_voltage3",
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"cpr_quotient1",
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"cpr_quotient2",
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"cpr_quotient3",
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"cpr_ring_osc1",
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"cpr_ring_osc2",
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"cpr_ring_osc3",
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"cpr_fuse_revision";
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};
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