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d7659d92eb
Nuke the remaining _nowl() stuff from the wakelock code in the form of __intel_de_wait_for_register_nowl(), and replace it with intel_de_wait_fw_us_atomic() that uses the low level _fw() register accessors in line with the rest of the code. No change in behaviour since wakelocks are only supported on xe, and xe doesn't have uncore.lock nor unclaimed register detection stuff. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-15-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
241 lines
5.5 KiB
C
241 lines
5.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "intel_display_core.h"
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#include "intel_dmc_wl.h"
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#include "intel_dsb.h"
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#include "intel_uncore.h"
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#include "intel_uncore_trace.h"
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static inline struct intel_uncore *__to_uncore(struct intel_display *display)
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{
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return to_intel_uncore(display->drm);
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}
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static inline u32
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intel_de_read(struct intel_display *display, i915_reg_t reg)
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{
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u32 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_read(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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static inline u8
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intel_de_read8(struct intel_display *display, i915_reg_t reg)
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{
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u8 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_read8(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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static inline u64
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intel_de_read64_2x32(struct intel_display *display,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u64 val;
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intel_dmc_wl_get(display, lower_reg);
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intel_dmc_wl_get(display, upper_reg);
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val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
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upper_reg);
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intel_dmc_wl_put(display, upper_reg);
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intel_dmc_wl_put(display, lower_reg);
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return val;
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}
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static inline void
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intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
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{
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intel_dmc_wl_get(display, reg);
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intel_uncore_posting_read(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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}
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static inline void
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intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
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{
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intel_dmc_wl_get(display, reg);
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intel_uncore_write(__to_uncore(display), reg, val);
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intel_dmc_wl_put(display, reg);
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}
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static inline u32
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intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
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{
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u32 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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static inline int
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intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_us,
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u32 *out_value)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
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value, timeout_us, 0, out_value);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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static inline int
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intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_ms,
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u32 *out_value)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
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value, 2, timeout_ms, out_value);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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static inline int
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intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_ms,
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u32 *out_value)
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{
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return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
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value, 2, timeout_ms, out_value);
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}
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static inline int
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intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout_us,
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u32 *out_value)
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{
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return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
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value, timeout_us, 0, out_value);
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}
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static inline int
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intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_us)
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{
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return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
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}
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static inline int
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intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_us)
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{
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return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
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}
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static inline int
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intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_ms)
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{
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return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
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}
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static inline int
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intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout_ms)
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{
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return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
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}
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(__to_uncore(display), reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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static inline void
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intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(__to_uncore(display), reg, val);
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}
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static inline u32
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intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
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{
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u32 old, val;
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old = intel_de_read_fw(display, reg);
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val = (old & ~clear) | set;
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intel_de_write_fw(display, reg, val);
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return old;
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}
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static inline u32
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intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
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{
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return intel_uncore_read_notrace(__to_uncore(display), reg);
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}
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static inline void
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intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
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{
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intel_uncore_write_notrace(__to_uncore(display), reg, val);
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}
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static __always_inline void
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intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
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i915_reg_t reg, u32 val)
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{
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if (dsb)
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intel_dsb_reg_write(dsb, reg, val);
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else
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intel_de_write_fw(display, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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