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49b5feb521
Add binding for Qualcom SM8750 Iris video codec, which comes with significantly different powering up sequence than previous SM8650, thus different clocks and resets. For consistency keep existing clock and clock-names naming, so the list shares common part. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> [bod: re-ordered patch title to dt-bindings: media] Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
187 lines
4.9 KiB
YAML
187 lines
4.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8750 SoC Iris video encoder and decoder
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maintainers:
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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The Iris video processing unit on Qualcomm SM8750 SoC is a video encode and
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decode accelerator.
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properties:
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compatible:
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enum:
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- qcom,sm8750-iris
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clocks:
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maxItems: 6
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clock-names:
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items:
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- const: iface # AXI0
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- const: core
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- const: vcodec0_core
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- const: iface1 # AXI1
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- const: core_freerun
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- const: vcodec0_core_freerun
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dma-coherent: true
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: cpu-cfg
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- const: video-mem
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iommus:
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maxItems: 2
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operating-points-v2: true
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opp-table:
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type: object
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power-domains:
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maxItems: 4
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power-domain-names:
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items:
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- const: venus
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- const: vcodec0
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- const: mxc
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- const: mmcx
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resets:
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maxItems: 4
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reset-names:
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items:
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- const: bus0
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- const: bus1
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- const: core
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- const: vcodec0_core
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required:
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- compatible
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- dma-coherent
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- interconnects
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- interconnect-names
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- iommus
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- power-domain-names
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- resets
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- reset-names
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allOf:
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- $ref: qcom,venus-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm8750-gcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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video-codec@aa00000 {
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compatible = "qcom,sm8750-iris";
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reg = <0x0aa00000 0xf0000>;
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clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
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<&videocc_mvs0c_clk>,
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<&videocc_mvs0_clk>,
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<&gcc GCC_VIDEO_AXI1_CLK>,
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<&videocc_mvs0c_freerun_clk>,
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<&videocc_mvs0_freerun_clk>;
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clock-names = "iface",
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"core",
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"vcodec0_core",
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"iface1",
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"core_freerun",
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"vcodec0_core_freerun";
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dma-coherent;
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iommus = <&apps_smmu 0x1940 0>,
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<&apps_smmu 0x1947 0>;
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "cpu-cfg",
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"video-mem";
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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operating-points-v2 = <&iris_opp_table>;
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memory-region = <&video_mem>;
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power-domains = <&videocc_mvs0c_gdsc>,
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<&videocc_mvs0_gdsc>,
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<&rpmhpd RPMHPD_MXC>,
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<&rpmhpd RPMHPD_MMCX>;
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power-domain-names = "venus",
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"vcodec0",
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"mxc",
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"mmcx";
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resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
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<&gcc GCC_VIDEO_AXI1_CLK_ARES>,
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<&videocc_mvs0c_freerun_clk_ares>,
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<&videocc_mvs0_freerun_clk_ares>;
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reset-names = "bus0",
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"bus1",
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"core",
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"vcodec0_core";
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iris_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-240000000 {
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opp-hz = /bits/ 64 <240000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>,
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<&rpmhpd_opp_low_svs_d1>;
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};
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opp-338000000 {
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opp-hz = /bits/ 64 <338000000>;
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required-opps = <&rpmhpd_opp_low_svs>,
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<&rpmhpd_opp_low_svs>;
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};
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opp-420000000 {
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opp-hz = /bits/ 64 <420000000>;
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required-opps = <&rpmhpd_opp_svs>,
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<&rpmhpd_opp_svs>;
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};
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opp-444000000 {
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opp-hz = /bits/ 64 <444000000>;
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required-opps = <&rpmhpd_opp_svs_l1>,
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<&rpmhpd_opp_svs_l1>;
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};
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opp-533333334 {
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opp-hz = /bits/ 64 <533333334>;
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required-opps = <&rpmhpd_opp_nom>,
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<&rpmhpd_opp_nom>;
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};
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opp-630000000 {
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opp-hz = /bits/ 64 <630000000>;
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required-opps = <&rpmhpd_opp_turbo>,
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<&rpmhpd_opp_turbo>;
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};
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};
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};
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