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Document new property arm,no-completion-irq . This optional property is intended for hardware that does not generate completion interrupts and can be used to unconditionally enable forced polling mode of operation. With this property set, such implementations which do not generate interrupts can be interacted with, until they are fixed to generate interrupts properly. Note that, because the original base protocol exchange also requires some sort of completion mechanism, it is not possible to query SCMI itself for this property and it must be described in DT. While this does look a bit like policy, the SCMI provider is part of the hardware, hence DT. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Message-Id: <20260117010241.186685-1-marek.vasut+renesas@mailbox.org> Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
600 lines
15 KiB
YAML
600 lines
15 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2021 ARM Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: System Control and Management Interface (SCMI) Message Protocol
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maintainers:
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- Sudeep Holla <sudeep.holla@arm.com>
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description: |
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The SCMI is intended to allow agents such as OSPM to manage various functions
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that are provided by the hardware platform it is running on, including power
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and performance functions.
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This binding is intended to define the interface the firmware implementing
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the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
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and Management Interface Platform Design Document")[0] provide for OSPM in
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the device tree.
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[0] https://developer.arm.com/documentation/den0056/latest
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anyOf:
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- $ref: /schemas/firmware/nxp,imx95-scmi.yaml
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properties:
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$nodename:
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pattern: '^scmi(-[0-9]+)?$'
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compatible:
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oneOf:
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- description: SCMI compliant firmware with mailbox transport
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items:
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- const: arm,scmi
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- description: SCMI compliant firmware with ARM SMC/HVC transport
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items:
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- const: arm,scmi-smc
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- description: SCMI compliant firmware with ARM SMC/HVC transport
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with shmem address(4KB-page, offset) as parameters
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items:
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- const: arm,scmi-smc-param
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- description: SCMI compliant firmware with Qualcomm SMC/HVC transport
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items:
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- const: qcom,scmi-smc
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- description: SCMI compliant firmware with SCMI Virtio transport.
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The virtio transport only supports a single device.
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items:
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- const: arm,scmi-virtio
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- description: SCMI compliant firmware with OP-TEE transport
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items:
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- const: linaro,scmi-optee
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interrupts:
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description:
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The interrupt that indicates message completion by the platform
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rather than by the return of the smc call. This should not be used
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except when the platform requires such behavior.
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maxItems: 1
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interrupt-names:
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const: a2p
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mbox-names:
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description:
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Specifies the mailboxes used to communicate with SCMI compliant
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firmware.
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oneOf:
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- items:
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- const: tx
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- const: rx
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minItems: 1
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- items:
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- const: tx
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- const: tx_reply
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- const: rx
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- const: rx_reply
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minItems: 2
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mboxes:
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description:
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List of phandle and mailbox channel specifiers. It should contain
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exactly one, two, three or four mailboxes; the first one or two for
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transmitting messages ("tx") and another optional ("rx") for receiving
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notifications and delayed responses, if supported by the platform.
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The optional ("rx_reply") is for notifications completion interrupt,
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if supported by the platform.
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The number of mailboxes needed for transmitting messages depends on the
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type of channels exposed by the specific underlying mailbox controller;
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one single channel descriptor is enough if such channel is bidirectional,
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while two channel descriptors are needed to represent the SCMI ("tx")
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channel if the underlying mailbox channels are of unidirectional type.
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The effective combination in numbers of mboxes and shmem descriptors let
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the SCMI subsystem determine unambiguosly which type of SCMI channels are
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made available by the underlying mailbox controller and how to use them.
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1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel
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2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels
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2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels
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3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels
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4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels
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Any other combination of mboxes and shmem is invalid.
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minItems: 1
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maxItems: 4
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shmem:
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description:
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List of phandle pointing to the shared memory(SHM) area, for each
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transport channel specified.
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minItems: 1
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maxItems: 2
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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atomic-threshold-us:
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description:
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An optional time value, expressed in microseconds, representing, on this
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platform, the threshold above which any SCMI command, advertised to have
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an higher-than-threshold execution latency, should not be considered for
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atomic mode of operation, even if requested.
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default: 0
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arm,max-rx-timeout-ms:
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description:
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An optional time value, expressed in milliseconds, representing the
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transport maximum timeout value for the receive channel. The value should
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be a non-zero value if set.
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minimum: 1
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arm,max-msg-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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An optional value, expressed in bytes, representing the maximum size
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allowed for the payload of messages transmitted on this transport.
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arm,max-msg:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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An optional value representing the maximum number of concurrent in-flight
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messages allowed by this transport; this number represents the maximum
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number of concurrently outstanding messages that the server can handle on
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this platform. If set, the value should be non-zero.
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minimum: 1
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arm,no-completion-irq:
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type: boolean
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description:
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This optional property is intended for hardware that does not generate
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completion interrupts and can be used to unconditionally enable forced
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polling mode of operation.
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arm,smc-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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SMC id required when using smc or hvc transports
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linaro,optee-channel-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Channel specifier required when using OP-TEE transport.
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protocol@11:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x11
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'#power-domain-cells':
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const: 1
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required:
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- '#power-domain-cells'
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protocol@12:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x12
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protocol@13:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x13
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'#clock-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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oneOf:
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- required:
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- '#clock-cells'
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- required:
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- '#power-domain-cells'
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protocol@14:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x14
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'#clock-cells':
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const: 1
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required:
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- '#clock-cells'
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protocol@15:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x15
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'#thermal-sensor-cells':
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const: 1
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required:
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- '#thermal-sensor-cells'
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protocol@16:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x16
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'#reset-cells':
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const: 1
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required:
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- '#reset-cells'
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protocol@17:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x17
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regulators:
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type: object
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additionalProperties: false
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description:
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The list of all regulators provided by this SCMI controller.
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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'^regulator@[0-9a-f]+$':
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type: object
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$ref: /schemas/regulator/regulator.yaml#
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unevaluatedProperties: false
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properties:
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reg:
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maxItems: 1
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description: Identifier for the voltage regulator.
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required:
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- reg
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protocol@18:
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$ref: '#/$defs/protocol-node'
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x18
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protocol@19:
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type: object
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allOf:
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- $ref: '#/$defs/protocol-node'
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- anyOf:
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- $ref: /schemas/pinctrl/pinctrl.yaml
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- $ref: /schemas/firmware/nxp,imx95-scmi-pinctrl.yaml
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unevaluatedProperties: false
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properties:
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reg:
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const: 0x19
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patternProperties:
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'-pins$':
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type: object
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allOf:
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- $ref: /schemas/pinctrl/pincfg-node.yaml#
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- $ref: /schemas/pinctrl/pinmux-node.yaml#
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unevaluatedProperties: false
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description:
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A pin multiplexing sub-node describes how to configure a
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set of pins in some desired function.
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A single sub-node may define several pin configurations.
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This sub-node is using the default pinctrl bindings to configure
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pin multiplexing and using SCMI protocol to apply a specified
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configuration.
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required:
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- reg
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unevaluatedProperties: false
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$defs:
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protocol-node:
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type: object
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description:
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Each sub-node represents a protocol supported. If the platform
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supports a dedicated communication channel for a particular protocol,
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then the corresponding transport properties must be present.
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The virtio transport does not support a dedicated communication channel.
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properties:
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reg:
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maxItems: 1
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mbox-names:
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oneOf:
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- items:
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- const: tx
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- const: rx
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minItems: 1
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- items:
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- const: tx
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- const: tx_reply
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- const: rx
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minItems: 2
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mboxes:
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minItems: 1
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maxItems: 3
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shmem:
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minItems: 1
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maxItems: 2
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linaro,optee-channel-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Channel specifier required when using OP-TEE transport and
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protocol has a dedicated communication channel.
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required:
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- reg
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required:
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- compatible
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if:
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properties:
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compatible:
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contains:
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const: arm,scmi
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then:
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properties:
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interrupts: false
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interrupt-names: false
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required:
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- mboxes
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- shmem
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else:
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properties:
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arm,no-completion-irq: false
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if:
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properties:
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compatible:
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contains:
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enum:
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- arm,scmi-smc
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- arm,scmi-smc-param
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- qcom,scmi-smc
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then:
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required:
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- arm,smc-id
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- shmem
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else:
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if:
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properties:
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compatible:
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contains:
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const: linaro,scmi-optee
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then:
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required:
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- linaro,optee-channel-id
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examples:
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- |
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firmware {
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scmi {
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compatible = "arm,scmi";
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mboxes = <&mhuB 0 0>,
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<&mhuB 0 1>;
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mbox-names = "tx", "rx";
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shmem = <&cpu_scp_lpri0>,
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<&cpu_scp_lpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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atomic-threshold-us = <10000>;
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#power-domain-cells = <1>;
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mboxes = <&mhuB 1 0>,
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<&mhuB 1 1>;
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mbox-names = "tx", "rx";
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shmem = <&cpu_scp_hpri0>,
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<&cpu_scp_hpri1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_sensors: protocol@15 {
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reg = <0x15>;
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#thermal-sensor-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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scmi_voltage: protocol@17 {
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reg = <0x17>;
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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regulator_devX: regulator@0 {
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reg = <0x0>;
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regulator-max-microvolt = <3300000>;
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};
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regulator_devY: regulator@9 {
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reg = <0x9>;
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <4200000>;
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};
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};
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};
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scmi_powercap: protocol@18 {
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reg = <0x18>;
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};
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scmi_pinctrl: protocol@19 {
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reg = <0x19>;
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i2c2-pins {
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groups = "g_i2c2_a", "g_i2c2_b";
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function = "f_i2c2";
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};
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mdio-pins {
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groups = "g_avb_mdio";
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drive-strength = <24>;
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};
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keys_pins: keys-pins {
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pins = "gpio_5_17", "gpio_5_20", "gpio_5_22", "gpio_2_1";
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bias-pull-up;
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};
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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sram@50000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x50000000 0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x50000000 0x10000>;
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cpu_scp_lpri0: scp-sram-section@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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cpu_scp_lpri1: scp-sram-section@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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cpu_scp_hpri0: scp-sram-section@100 {
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compatible = "arm,scmi-shmem";
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reg = <0x100 0x80>;
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};
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cpu_scp_hpri2: scp-sram-section@180 {
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compatible = "arm,scmi-shmem";
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reg = <0x180 0x80>;
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};
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};
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};
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- |
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firmware {
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scmi {
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compatible = "arm,scmi-smc";
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shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
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arm,smc-id = <0xc3000001>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_devpd1: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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};
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};
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- |
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firmware {
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scmi {
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compatible = "linaro,scmi-optee";
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linaro,optee-channel-id = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs1: protocol@13 {
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reg = <0x13>;
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linaro,optee-channel-id = <1>;
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shmem = <&cpu_optee_lpri0>;
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#power-domain-cells = <1>;
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};
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scmi_clk0: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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sram@51000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x51000000 0x0 0x10000>;
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#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0x51000000 0x10000>;
|
|
|
|
cpu_optee_lpri0: optee-sram-section@0 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x0 0x80>;
|
|
};
|
|
};
|
|
};
|
|
|
|
...
|