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0b7973dfb7
Add compatible string for the interrupt steering controller used in NXP S32N79 SoC. The S32N79 SoC differs from the i.MX version by not implementing the CHANCTRL register, but otherwise maintains the same programming model and register layout. Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
119 lines
2.8 KiB
YAML
119 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IRQSTEER Interrupt Multiplexer
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx-irqsteer
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- nxp,s32n79-irqsteer
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- items:
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- enum:
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- fsl,imx8m-irqsteer
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- fsl,imx8mp-irqsteer
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- fsl,imx8qm-irqsteer
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- fsl,imx8qxp-irqsteer
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- fsl,imx94-irqsteer
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- fsl,imx95-irqsteer
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- const: fsl,imx-irqsteer
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reg:
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maxItems: 1
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interrupts:
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description: |
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should contain the up to 8 parent interrupt lines used to multiplex
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the input interrupts. They should be specified sequentially from
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output 0 to 7.
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items:
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- description: output interrupt 0
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- description: output interrupt 1
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- description: output interrupt 2
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- description: output interrupt 3
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- description: output interrupt 4
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- description: output interrupt 5
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- description: output interrupt 6
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- description: output interrupt 7
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minItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: ipg
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power-domains:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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fsl,channel:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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u32 value representing the output channel that all input IRQs should be
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steered into.
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fsl,num-irqs:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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u32 value representing the number of input interrupts of this channel,
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should be multiple of 32 input interrupts and up to 512 interrupts.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- interrupt-controller
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- "#interrupt-cells"
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- fsl,channel
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- fsl,num-irqs
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8mp-irqsteer
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- fsl,imx8qm-irqsteer
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- fsl,imx8qxp-irqsteer
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- fsl,imx95-irqsteer
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then:
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required:
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- power-domains
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else:
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properties:
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power-domains: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mq-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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interrupt-controller@32e2d000 {
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compatible = "fsl,imx-irqsteer";
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reg = <0x32e2d000 0x1000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
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clock-names = "ipg";
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fsl,channel = <0>;
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fsl,num-irqs = <64>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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