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Document RZ/G3L (R9A08G046) IRQC. The IRQC block on the RZ/G3L SoC is nearly identical to that found on the RZ/G3S SoC, with the following differences: it supports more external interrupts and GPT error interrupts, and adds registers for GPT/MTU interrupt selection and shared interrupt selection between external interrupt and TINT. A new compatible string "renesas,r9a08g046-irqc" is therefore introduced for the RZ/G3L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260325192451.172562-3-biju.das.jz@bp.renesas.com
238 lines
8.0 KiB
YAML
238 lines
8.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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IA55 performs various interrupt controls including synchronization for the external
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interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
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interrupts output by each IP. And it notifies the interrupt to the GIC
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- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
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- GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
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- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
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stand-up edge detection interrupts)
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,r9a07g043u-irqc # RZ/G2UL
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- renesas,r9a07g044-irqc # RZ/G2{L,LC}
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- renesas,r9a07g054-irqc # RZ/V2L
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- renesas,r9a08g045-irqc # RZ/G3S
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- const: renesas,rzg2l-irqc
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- enum:
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- renesas,r9a07g043f-irqc # RZ/Five
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- renesas,r9a08g046-irqc # RZ/G3L
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'#interrupt-cells':
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description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
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include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
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cell is used to specify the flag.
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const: 2
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'#address-cells':
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const: 0
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interrupt-controller: true
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reg:
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maxItems: 1
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interrupts:
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minItems: 45
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maxItems: 61
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interrupt-names:
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minItems: 45
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maxItems: 61
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items:
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oneOf:
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- description: NMI interrupt
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const: nmi
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- description: External IRQ interrupt
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pattern: '^irq([0-9]|1[0-5])$'
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- description: GPIO interrupt
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pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$'
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- description: Bus error interrupt
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const: bus-err
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- description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
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const: ec7tie1-0
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- description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
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const: ec7tie2-0
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- description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
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const: ec7tiovf-0
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- description: ECCRAM1 1bit error interrupt
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const: ec7tie1-1
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- description: ECCRAM1 2bit error interrupt
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const: ec7tie2-1
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- description: ECCRAM1 error overflow interrupt
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const: ec7tiovf-1
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- description: Integrated GPT Error interrupt
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pattern: '^ovfunf([0-7])$'
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: clk
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- const: pclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- power-domains
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- resets
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a07g043f-irqc
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- renesas,r9a07g043u-irqc
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- renesas,r9a07g044-irqc
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- renesas,r9a07g054-irqc
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then:
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properties:
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interrupts:
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minItems: 48
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maxItems: 48
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interrupt-names:
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minItems: 48
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maxItems: 48
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a08g045-irqc
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then:
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properties:
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interrupts:
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maxItems: 45
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interrupt-names:
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maxItems: 45
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a08g046-irqc
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then:
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properties:
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interrupts:
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minItems: 61
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interrupt-names:
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minItems: 61
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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irqc: interrupt-controller@110a0000 {
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compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
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reg = <0x110a0000 0x10000>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "nmi",
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"irq0", "irq1", "irq2", "irq3",
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"irq4", "irq5", "irq6", "irq7",
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"tint0", "tint1", "tint2", "tint3",
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"tint4", "tint5", "tint6", "tint7",
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"tint8", "tint9", "tint10", "tint11",
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"tint12", "tint13", "tint14", "tint15",
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"tint16", "tint17", "tint18", "tint19",
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"tint20", "tint21", "tint22", "tint23",
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"tint24", "tint25", "tint26", "tint27",
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"tint28", "tint29", "tint30", "tint31",
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"bus-err", "ec7tie1-0", "ec7tie2-0",
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"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
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"ec7tiovf-1";
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clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
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<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
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clock-names = "clk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_IA55_RESETN>;
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};
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