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Document the bindings for the memory controller found on Tegra210 SoCs. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
78 lines
1.8 KiB
YAML
78 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra210 SoC Memory Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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description: |
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The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split
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into two 32 bit channels to support LPDDR3 and LPDDR4 with x16 subpartitions.
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The MC handles memory requests for 34-bit virtual addresses from internal
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clients and arbitrates among them to allocate memory bandwidth.
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Up to 8 GiB of physical memory can be supported. Security features such as
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encryption of traffic to and from DRAM via general security apertures are
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available for video and other secure applications.
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properties:
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$nodename:
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pattern: "^memory-controller@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- nvidia,tegra210-mc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: module clock
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clock-names:
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items:
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- const: mc
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"#iommu-cells":
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#iommu-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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memory-controller@70019000 {
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compatible = "nvidia,tegra210-mc";
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reg = <0x70019000 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_MC>;
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clock-names = "mc";
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#iommu-cells = <1>;
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#reset-cells = <1>;
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};
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