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Describe JH7110 SoC DDR external memory interface. Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
75 lines
1.5 KiB
YAML
75 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 DMC
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maintainers:
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- E Shattow <e@freeshell.de>
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description:
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JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
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2133Mbps (up to 2800Mbps).
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properties:
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compatible:
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items:
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- const: starfive,jh7110-dmc
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reg:
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items:
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- description: controller registers
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- description: phy registers
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: pll
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resets:
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items:
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- description: axi
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- description: osc
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- description: apb
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reset-names:
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items:
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- const: axi
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- const: osc
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- const: apb
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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memory-controller@15700000 {
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compatible = "starfive,jh7110-dmc";
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reg = <0x0 0x15700000 0x0 0x10000>,
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<0x0 0x13000000 0x0 0x10000>;
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clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
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clock-names = "pll";
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resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
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<&syscrg JH7110_SYSRST_DDR_OSC>,
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<&syscrg JH7110_SYSRST_DDR_APB>;
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reset-names = "axi", "osc", "apb";
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};
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};
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