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Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Only one example is required in the DTS bindings YAML file. Signed-off-by: Randolph Lin <randolph@andestech.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260225085504.3757601-2-randolph@andestech.com
90 lines
2.1 KiB
YAML
90 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes QiLai PCIe host controller
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description:
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Andes QiLai PCIe host controller is based on the Synopsys DesignWare
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PCI core.
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maintainers:
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- Randolph Lin <randolph@andestech.com>
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: andestech,qilai-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: APB registers.
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- description: PCIe configuration space region.
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reg-names:
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items:
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- const: dbi
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- const: apb
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- const: config
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dma-coherent: true
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ranges:
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maxItems: 2
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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required:
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@80000000 {
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compatible = "andestech,qilai-pcie";
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device_type = "pci";
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reg = <0x0 0x80000000 0x0 0x20000000>,
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<0x0 0x04000000 0x0 0x00001000>,
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<0x0 0x00000000 0x0 0x00010000>;
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reg-names = "dbi", "apb", "config";
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dma-coherent;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
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<0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>;
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#interrupt-cells = <1>;
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interrupts = <0xf>;
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interrupt-names = "msi";
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interrupt-parent = <&plic0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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...
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