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On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Reviewed-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
104 lines
3.6 KiB
YAML
104 lines
3.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-irqmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Polarfire SoC GPIO Interrupt Mux
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description: |
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There are 3 GPIO controllers on this SoC, of which:
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- GPIO controller 0 has 14 GPIOs
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- GPIO controller 1 has 24 GPIOs
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- GPIO controller 2 has 32 GPIOs
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All GPIOs are capable of generating interrupts, for a total of 70.
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There are only 41 IRQs available however, so a configurable mux is used to
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ensure all GPIOs can be used for interrupt generation.
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38 of the 41 interrupts are in what the documentation calls "direct mode",
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as they provide an exclusive connection from a GPIO to the PLIC.
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Lines 18 to 23 on GPIO controller 1 are always in "direct mode".
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The 3 remaining interrupts are used to mux the interrupts which do not have
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a exclusive connection, one for each GPIO controller.
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properties:
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compatible:
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const: microchip,mpfs-irqmux
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reg:
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maxItems: 1
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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interrupt-map-mask:
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items:
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- const: 0x7f
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interrupt-map:
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description: |
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Specifies the mapping from GPIO interrupt lines to plic interrupts.
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The child interrupt number set in arrays items is computed using the
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following formula:
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gpio_bank * 32 + gpio_number
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with:
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- gpio_bank: The GPIO bank number
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- 0 for GPIO0,
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- 1 for GPIO1,
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- 2 for GPIO2
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- gpio_number: Number of the gpio in the bank (0..31)
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maxItems: 70
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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additionalProperties: false
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examples:
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- |
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interrupt-controller@54 {
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compatible = "microchip,mpfs-irqmux";
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reg = <0x54 0x4>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x7f>;
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interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
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<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
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<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
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<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
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<12 &plic 25>, <13 &plic 26>,
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<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
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<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
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<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
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<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
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<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
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<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
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<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
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<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
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<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
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<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
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<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
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<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
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<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
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<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
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<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
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<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
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<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
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<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
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<94 &plic 53>, <95 &plic 53>;
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};
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