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96f06d055c
This binding documented clock-names, but never bothered to document what the name should be, rendering the property useless to software. It's not a required property, so it can just be removed without harming any software that conjured up it's own name for the clock, as they could not rely on it being there to begin with. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-spoils-snowbird-99f6e3a2dae3@spud Signed-off-by: Mark Brown <broonie@kernel.org>
153 lines
3.4 KiB
YAML
153 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip FPGA {Q,}SPI Controllers
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description:
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SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
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fabric IP cores they are based on
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- microchip,mpfs-qspi
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- microchip,pic64gx-qspi
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- const: microchip,coreqspi-rtl-v2
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- enum:
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- microchip,coreqspi-rtl-v2 # FPGA QSPI
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- microchip,corespi-rtl-v5 # FPGA CoreSPI
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- microchip,mpfs-spi
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- items:
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- const: microchip,pic64gx-spi
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- const: microchip,mpfs-spi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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microchip,apb-datawidth:
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description: APB bus data width in bits.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16, 32]
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default: 8
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microchip,frame-size:
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description: |
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Number of bits per SPI frame, as configured in Libero.
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In Motorola and TI modes, this corresponds directly
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to the requested frame size. For NSC mode this is set
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to 9 + the required data frame size.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 4
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maximum: 32
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default: 8
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microchip,protocol-configuration:
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description: CoreSPI protocol selection. Determines operating mode
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- motorola
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- ti
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- nsc
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default: motorola
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microchip,motorola-mode:
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description: Motorola SPI mode selection
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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default: 3
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microchip,ssel-active:
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description: |
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Keep SSEL asserted between frames when using the Motorola protocol.
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When present, the controller keeps SSEL active across contiguous
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transfers and deasserts only when the overall transfer completes.
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type: boolean
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: microchip,mpfs-spi
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then:
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properties:
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num-cs:
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default: 1
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- if:
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properties:
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compatible:
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contains:
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const: microchip,mpfs-spi
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not:
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required:
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- cs-gpios
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then:
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properties:
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num-cs:
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maximum: 1
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- if:
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properties:
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compatible:
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contains:
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const: microchip,corespi-rtl-v5
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then:
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properties:
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num-cs:
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minimum: 1
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maximum: 8
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default: 8
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fifo-depth:
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minimum: 1
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maximum: 32
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default: 4
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else:
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properties:
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microchip,apb-datawidth: false
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microchip,frame-size: false
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microchip,protocol-configuration: false
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microchip,motorola-mode: false
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microchip,ssel-active: false
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unevaluatedProperties: false
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examples:
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- |
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#include "dt-bindings/clock/microchip,mpfs-clock.h"
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spi@20108000 {
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compatible = "microchip,mpfs-spi";
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reg = <0x20108000 0x1000>;
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clocks = <&clkcfg CLK_SPI0>;
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interrupt-parent = <&plic>;
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interrupts = <54>;
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};
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...
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