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Change spi-rx-bus-width and spi-tx-bus-width properties from single uint32 values to arrays of uint32 values. This allows describing SPI peripherals connected to controllers that have multiple data lanes for receiving or transmitting two or more words in parallel. Each index in the array corresponds to a physical data lane (one or more wires depending on the bus width). Additional mapping properties will be needed in cases where a lane on the controller or peripheral is skipped. Bindings that make use of this property are updated in the same commit to avoid validation errors. The adi,ad4030 binding can now better describe the chips multi-lane capabilities, so that binding is refined and gets a new example. Converting from single uint32 to array of uint32 does not break .dts/ .dtb files since there is no difference between specifying a single uint32 value and an array with a single uint32 value in devicetree. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-1-12af183c06eb@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
114 lines
2.3 KiB
YAML
114 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra Quad SPI Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jonathan Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra210-qspi
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- nvidia,tegra186-qspi
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- nvidia,tegra194-qspi
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- nvidia,tegra234-qspi
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- nvidia,tegra241-qspi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: qspi
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- const: qspi_out
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clocks:
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maxItems: 2
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resets:
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maxItems: 1
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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iommus:
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maxItems: 1
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patternProperties:
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"@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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spi-rx-bus-width:
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items:
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- enum: [1, 2, 4]
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spi-tx-bus-width:
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items:
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- enum: [1, 2, 4]
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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- resets
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unevaluatedProperties: false
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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not:
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contains:
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const: nvidia,tegra234-qspi
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then:
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properties:
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iommus: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/reset/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@70410000 {
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compatible = "nvidia,tegra210-qspi";
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reg = <0x70410000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA210_CLK_QSPI>,
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<&tegra_car TEGRA210_CLK_QSPI_PM>;
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clock-names = "qspi", "qspi_out";
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resets = <&tegra_car 211>;
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dmas = <&apbdma 5>, <&apbdma 5>;
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dma-names = "rx", "tx";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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nvidia,tx-clk-tap-delay = <0>;
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nvidia,rx-clk-tap-delay = <0>;
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};
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};
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