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eea1a28f93
Commit c056718464 ("openrisc: sleep instead of spin on secondary
wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never
achieved on FPGA development boards. This is because the above patch
has a step to unmask IPIs on non-boot cpu's but on hardware without
power management, IPIs remain masked.
This meant that IPI's were never actually working on the simple SMP
systems we run on development boards. The systems booted but stability
was very suspect.
Add the ability to unmask IPI's on the non-boot cores. This is done by
making the OMPIC IRQs proper percpu IRQs. We can then use the
enabled_percpu_irq() to unmask IRQ on the non-boot cpus.
Update the or1k PIC driver to use a flow handler that can switch between
percpu and the configured level or edge flow handlers at runtime.
This mechanism is inspired by that done in the J-Core AIC driver.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Acked-by: Thomas Gleixner <tglx@kernel.org>
28 lines
850 B
C
28 lines
850 B
C
/*
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* Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_OPENRISC_SMP_H
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#define __ASM_OPENRISC_SMP_H
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#include <asm/spr.h>
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#include <asm/spr_defs.h>
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#define raw_smp_processor_id() (current_thread_info()->cpu)
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#define hard_smp_processor_id() mfspr(SPR_COREID)
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extern void smp_init_cpus(void);
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extern void arch_send_call_function_single_ipi(int cpu);
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extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
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extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int),
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unsigned int irq);
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extern void handle_IPI(unsigned int ipi_msg);
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#endif /* __ASM_OPENRISC_SMP_H */
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