mirror of
https://github.com/torvalds/linux.git
synced 2026-04-19 15:24:02 -04:00
1ef893e274
[Why] When hotplug a HDMI monitor during entering S0i3 or DPMSOFF state due to entering infinite loop when calling vbios to program pixel clocks. In this scenario, pll is enabled but phy is not, and there is not a programing guide for this case. [How] Before we having the proper programing guide, before disable pll, doing a phy enable and disable to avoid the issue. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
51 lines
1.7 KiB
C
51 lines
1.7 KiB
C
/*
|
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*
|
|
* Authors: AMD
|
|
*
|
|
*/
|
|
|
|
#ifndef __DC_HWSS_DCN21_H__
|
|
#define __DC_HWSS_DCN21_H__
|
|
|
|
#include "hw_sequencer_private.h"
|
|
|
|
struct dc;
|
|
|
|
int dcn21_init_sys_ctx(struct dce_hwseq *hws,
|
|
struct dc *dc,
|
|
struct dc_phy_addr_space_config *pa_config);
|
|
|
|
bool dcn21_s0i3_golden_init_wa(struct dc *dc);
|
|
|
|
void dcn21_exit_optimized_pwr_state(
|
|
const struct dc *dc,
|
|
struct dc_state *context);
|
|
|
|
void dcn21_optimize_pwr_state(
|
|
const struct dc *dc,
|
|
struct dc_state *context);
|
|
|
|
void dcn21_PLAT_58856_wa(struct dc_state *context,
|
|
struct pipe_ctx *pipe_ctx);
|
|
|
|
#endif /* __DC_HWSS_DCN21_H__ */
|