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ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include <subdev/acr.h>
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#include <nvfw/flcn.h>
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static void
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gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct flcn_bl_dmem_desc_v2 hdr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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hdr.code_dma_base = hdr.code_dma_base + adjust;
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hdr.data_dma_base = hdr.data_dma_base + adjust;
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
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}
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static void
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gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const u64 base = lsfw->offset.img + lsfw->app_start_offset;
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const u64 code = base + lsfw->app_resident_code_offset;
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const u64 data = base + lsfw->app_resident_data_offset;
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const struct flcn_bl_dmem_desc_v2 hdr = {
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.ctx_dma = FALCON_DMAIDX_UCODE,
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.code_dma_base = code,
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.non_sec_code_off = lsfw->app_resident_code_offset,
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.non_sec_code_size = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = data,
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.data_size = lsfw->app_resident_data_size,
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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const struct nvkm_acr_lsf_func
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gp108_gr_gpccs_acr = {
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.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp108_gr_acr_bld_write,
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.bld_patch = gp108_gr_acr_bld_patch,
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};
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const struct nvkm_acr_lsf_func
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gp108_gr_fecs_acr = {
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp108_gr_acr_bld_write,
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.bld_patch = gp108_gr_acr_bld_patch,
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};
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MODULE_FIRMWARE("nvidia/gp108/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin");
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static const struct gf100_gr_fwif
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gp108_gr_fwif[] = {
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{ 0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
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{}
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};
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int
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gp108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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{
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return gf100_gr_new_(gp108_gr_fwif, device, index, pgr);
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}
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