Thierry Reding 0d0d498265 drm/nouveau/ltc/gp10b: Add custom L2 cache implementation ...

There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

2020-01-15 10:49:59 +10:00

..

base.c

drm/nouveau/gr/gp102-: setup stencil zbc

2018-05-18 15:01:26 +10:00

gf100.c

drm/nouveau/ltc/gm200: limit NV_MMU_PTE_COMPTAGLINE bits to 16 where required

2017-11-02 13:32:27 +10:00

gk104.c

drm/nouveau/ltc/gf100: add flush/invalidate functions

2015-11-03 15:02:18 +10:00

gm107.c

drm/nouveau/ltc/gp100: initial support

2016-07-14 11:53:25 +10:00

gm200.c

drm/nouveau/ltc/gm107-: fix typo in the address of NV_PLTCG_LTC0_LTS0_INTR

2016-06-02 13:53:38 +10:00

gp10b.c

drm/nouveau/ltc/gp10b: Add custom L2 cache implementation

2020-01-15 10:49:59 +10:00

gp100.c

drm/nouveau/gr/gp102-: setup stencil zbc

2018-05-18 15:01:26 +10:00

gp102.c

drm/nouveau/gr/gp102-: setup stencil zbc

2018-05-18 15:01:26 +10:00

Kbuild

drm/nouveau/ltc/gp10b: Add custom L2 cache implementation

2020-01-15 10:49:59 +10:00

priv.h

drm/nouveau/ltc/gp10b: Add custom L2 cache implementation

2020-01-15 10:49:59 +10:00