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22dcda45a3
ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef __NVKM_PMU_PRIV_H__
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#define __NVKM_PMU_PRIV_H__
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#define nvkm_pmu(p) container_of((p), struct nvkm_pmu, subdev)
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#include <subdev/pmu.h>
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#include <subdev/pmu/fuc/os.h>
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enum nvkm_acr_lsf_id;
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struct nvkm_acr_lsfw;
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struct nvkm_pmu_func {
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const struct nvkm_falcon_func *flcn;
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struct {
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u32 *data;
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u32 size;
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} code;
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struct {
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u32 *data;
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u32 size;
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} data;
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bool (*enabled)(struct nvkm_pmu *);
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void (*reset)(struct nvkm_pmu *);
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int (*init)(struct nvkm_pmu *);
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void (*fini)(struct nvkm_pmu *);
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void (*intr)(struct nvkm_pmu *);
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int (*send)(struct nvkm_pmu *, u32 reply[2], u32 process,
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u32 message, u32 data0, u32 data1);
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void (*recv)(struct nvkm_pmu *);
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int (*initmsg)(struct nvkm_pmu *);
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void (*pgob)(struct nvkm_pmu *, bool);
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};
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extern const struct nvkm_falcon_func gt215_pmu_flcn;
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int gt215_pmu_init(struct nvkm_pmu *);
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void gt215_pmu_fini(struct nvkm_pmu *);
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void gt215_pmu_intr(struct nvkm_pmu *);
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void gt215_pmu_recv(struct nvkm_pmu *);
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int gt215_pmu_send(struct nvkm_pmu *, u32[2], u32, u32, u32, u32);
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bool gf100_pmu_enabled(struct nvkm_pmu *);
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void gf100_pmu_reset(struct nvkm_pmu *);
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void gk110_pmu_pgob(struct nvkm_pmu *, bool);
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void gm20b_pmu_acr_bld_patch(struct nvkm_acr *, u32, s64);
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void gm20b_pmu_acr_bld_write(struct nvkm_acr *, u32, struct nvkm_acr_lsfw *);
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int gm20b_pmu_acr_boot(struct nvkm_falcon *);
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int gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *, enum nvkm_acr_lsf_id);
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void gm20b_pmu_recv(struct nvkm_pmu *);
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int gm20b_pmu_initmsg(struct nvkm_pmu *);
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struct nvkm_pmu_fwif {
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int version;
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int (*load)(struct nvkm_pmu *, int ver, const struct nvkm_pmu_fwif *);
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const struct nvkm_pmu_func *func;
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const struct nvkm_acr_lsf_func *acr;
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};
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int gf100_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *);
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int gm20b_pmu_load(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *);
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int nvkm_pmu_ctor(const struct nvkm_pmu_fwif *, struct nvkm_device *,
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int index, struct nvkm_pmu *);
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int nvkm_pmu_new_(const struct nvkm_pmu_fwif *, struct nvkm_device *,
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int index, struct nvkm_pmu **);
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#endif
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