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b4156204e0
Add DT bindings for the peripheral clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251212022619.3072132-4-jian.hu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
117 lines
3.0 KiB
YAML
117 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic T7 Peripherals Clock Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Xianwei Zhao <xianwei.zhao@amlogic.com>
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- Jian Hu <jian.hu@amlogic.com>
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properties:
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compatible:
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const: amlogic,t7-peripherals-clkc
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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minItems: 14
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items:
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- description: input oscillator
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- description: input sys clk
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- description: input fixed pll
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- description: input fclk div 2
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- description: input fclk div 2p5
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- description: input fclk div 3
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- description: input fclk div 4
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- description: input fclk div 5
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- description: input fclk div 7
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- description: input hifi pll
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- description: input gp0 pll
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- description: input gp1 pll
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- description: input mpll1
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- description: input mpll2
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- description: external input rmii oscillator (optional)
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- description: input video pll0 (optional)
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- description: external pad input for rtc (optional)
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clock-names:
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minItems: 14
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items:
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- const: xtal
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- const: sys
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- const: fix
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- const: fdiv2
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- const: fdiv2p5
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- const: fdiv3
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- const: fdiv4
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- const: fdiv5
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- const: fdiv7
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- const: hifi
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- const: gp0
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- const: gp1
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- const: mpll1
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- const: mpll2
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- const: ext_rmii
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- const: vid_pll0
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- const: ext_rtc
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clkc_periphs:clock-controller@0 {
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compatible = "amlogic,t7-peripherals-clkc";
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reg = <0 0x0 0 0x1c8>;
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#clock-cells = <1>;
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clocks = <&xtal>,
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<&scmi_clk 13>,
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<&scmi_clk 16>,
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<&scmi_clk 18>,
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<&scmi_clk 20>,
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<&scmi_clk 22>,
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<&scmi_clk 24>,
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<&scmi_clk 26>,
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<&scmi_clk 28>,
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<&hifi 1>,
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<&gp0 1>,
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<&gp1 1>,
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<&mpll 4>,
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<&mpll 6>;
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clock-names = "xtal",
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"sys",
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"fix",
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"fdiv2",
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"fdiv2p5",
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"fdiv3",
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"fdiv4",
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"fdiv5",
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"fdiv7",
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"hifi",
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"gp0",
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"gp1",
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"mpll1",
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"mpll2";
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};
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};
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