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a2ed1aed68
The PCIESYS register space contains a pure clock controller, which has no system controller register, so this definitely doesn't need any "syscon" compatible. As a side note, luckily no devicetree ever added the syscon string to PCIESYS clock controller node compatibles, so this also resolves a dtbs_check warning for mt7622. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
46 lines
946 B
YAML
46 lines
946 B
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIESYS clock and reset controller
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description:
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The MediaTek PCIESYS controller provides various clocks to the system.
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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properties:
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compatible:
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enum:
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- mediatek,mt7622-pciesys
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- mediatek,mt7629-pciesys
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
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"#reset-cells":
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const: 1
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required:
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@1a100800 {
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compatible = "mediatek,mt7622-pciesys";
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reg = <0x1a100800 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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