mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 14:53:58 -04:00
fe6262910c
Some IOMMUs on some platforms (there doesn't seem to be a good denominator
for this) require the presence of a third clock, specifically relating
to the instance's Translation Buffer Unit (TBU).
Stephan Gerhold noted [1] that according to Qualcomm Snapdragon 410E
Processor (APQ8016E) Technical Reference Manual, SMMU chapter, section
"8.8.3.1.2 Clock gating", which reads:
For APPS TCU/TBU (TBU to TCU interface is asynchronous)
Software should turn ON clock to APPS TCU
- During APPS TCU register programming sequence
For GPU TCU/TBU (TBU to TCU interface is synchronous)
Software should turn ON clock to GPU TBU
- During GPU TLB invalidation sequence <=====================
Software should turn ON clock to GPU TCU
- During GPU TCU register programming sequence
- While GPU master clock is Active
The clock should be turned on at least during TLB invalidation on the
GPU SMMU instance. This is corroborated by Commit 5bc1cf1466
("iommu/qcom: add optional 'tbu' clock for TLB invalidate").
This is also not to be confused with qcom,sdm845-tbu, which is a
description of a debug interface, absent on the generation of hardware
that this binding describes.
Allow this clock.
[1] https://lore.kernel.org/linux-arm-msm/aPX_cKtial56AgvU@linaro.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
133 lines
3.0 KiB
YAML
133 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm Technologies legacy IOMMU implementations
|
|
|
|
maintainers:
|
|
- Konrad Dybcio <konradybcio@kernel.org>
|
|
|
|
description: |
|
|
Qualcomm "B" family devices which are not compatible with arm-smmu have
|
|
a similar looking IOMMU, but without access to the global register space
|
|
and optionally requiring additional configuration to route context IRQs
|
|
to non-secure vs secure interrupt line.
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- items:
|
|
- enum:
|
|
- qcom,msm8916-iommu
|
|
- qcom,msm8917-iommu
|
|
- qcom,msm8937-iommu
|
|
- qcom,msm8953-iommu
|
|
- const: qcom,msm-iommu-v1
|
|
- items:
|
|
- enum:
|
|
- qcom,msm8953-iommu
|
|
- qcom,msm8976-iommu
|
|
- const: qcom,msm-iommu-v2
|
|
|
|
clocks:
|
|
minItems: 2
|
|
items:
|
|
- description: Clock required for IOMMU register group access
|
|
- description: Clock required for underlying bus access
|
|
- description: Clock required for Translation Buffer Unit access
|
|
|
|
clock-names:
|
|
minItems: 2
|
|
items:
|
|
- const: iface
|
|
- const: bus
|
|
- const: tbu
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
ranges: true
|
|
|
|
qcom,iommu-secure-id:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
The SCM secure ID of the IOMMU instance.
|
|
|
|
'#address-cells':
|
|
const: 1
|
|
|
|
'#size-cells':
|
|
const: 1
|
|
|
|
'#iommu-cells':
|
|
const: 1
|
|
|
|
patternProperties:
|
|
"^iommu-ctx@[0-9a-f]+$":
|
|
type: object
|
|
additionalProperties: false
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- qcom,msm-iommu-v1-ns
|
|
- qcom,msm-iommu-v1-sec
|
|
- qcom,msm-iommu-v2-ns
|
|
- qcom,msm-iommu-v2-sec
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
qcom,ctx-asid:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
The ASID number associated to the context bank.
|
|
|
|
required:
|
|
- compatible
|
|
- interrupts
|
|
- reg
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
- clock-names
|
|
- ranges
|
|
- '#address-cells'
|
|
- '#size-cells'
|
|
- '#iommu-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
apps_iommu: iommu@1e20000 {
|
|
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
|
|
reg = <0x01ef0000 0x3000>;
|
|
clocks = <&gcc GCC_SMMU_CFG_CLK>,
|
|
<&gcc GCC_APSS_TCU_CLK>;
|
|
clock-names = "iface", "bus";
|
|
qcom,iommu-secure-id = <17>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
#iommu-cells = <1>;
|
|
ranges = <0 0x01e20000 0x40000>;
|
|
|
|
/* mdp_0: */
|
|
iommu-ctx@4000 {
|
|
compatible = "qcom,msm-iommu-v1-ns";
|
|
reg = <0x4000 0x1000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|