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0d95880395
The S32 chipsets have a GPR region which has a miscellaneous registers including the GMAC_0_CTRL_STS register. Originally, this code accessed that register in a sort of ad-hoc way, but it's cleaner to use a syscon interface to access these registers. We still need to maintain the old method of accessing the GMAC register but using a syscon will let us access other registers more cleanly. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/3b75e950b2f8faecd1a9fa757e7eb7b42ace838f.1769764941.git.dan.carpenter@linaro.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
119 lines
3.1 KiB
YAML
119 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2021-2024 NXP
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
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maintainers:
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- Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
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description:
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This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
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The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
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the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
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interface over Pinctrl device or the output can be routed
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to the embedded SerDes for SGMII connectivity.
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properties:
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compatible:
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oneOf:
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- const: nxp,s32g2-dwmac
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- items:
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- enum:
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- nxp,s32g3-dwmac
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- nxp,s32r45-dwmac
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- const: nxp,s32g2-dwmac
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reg:
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items:
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- description: Main GMAC registers
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- description: GMAC PHY mode control register
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nxp,phy-sel:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to the GPR syscon node
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- description: offset of PHY selection register
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description:
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This phandle points to the GMAC_0_CTRL_STS register which controls the
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GMAC_0 configuration options. The register lets you select the PHY
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interface and the PHY mode. It also controls if the FTM_0 or FTM_1
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FlexTimer Modules connect to GMAC_0.
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interrupts:
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maxItems: 1
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interrupt-names:
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const: macirq
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clocks:
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items:
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- description: Main GMAC clock
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- description: Transmit clock
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- description: Receive clock
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- description: PTP reference clock
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clock-names:
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items:
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- const: stmmaceth
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- const: tx
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- const: rx
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- const: ptp_ref
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required:
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- clocks
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- clock-names
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allOf:
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- $ref: snps,dwmac.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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ethernet@4033c000 {
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compatible = "nxp,s32g2-dwmac";
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reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
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<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
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nxp,phy-sel = <&gpr 0x4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
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clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <5>;
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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};
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