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Add binding for the OTP controller found on Google GS101. Reviewed-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://patch.msgid.link/20251222-gs101-chipid-v4-1-aa8e20ce7bb3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
62 lines
1.3 KiB
YAML
62 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Google GS101 OTP Controller
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maintainers:
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- Tudor Ambarus <tudor.ambarus@linaro.org>
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description: |
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OTP controller drives a NVMEM memory where system or user specific data
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can be stored. The OTP controller register space is of interest as well
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because it contains dedicated registers where it stores the Product ID
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and the Chip ID (apart other things like TMU or ASV info).
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allOf:
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- $ref: nvmem.yaml#
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properties:
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compatible:
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items:
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- const: google,gs101-otp
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clocks:
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maxItems: 1
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clock-names:
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const: pclk
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/google,gs101.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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efuse@10000000 {
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compatible = "google,gs101-otp";
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reg = <0x10000000 0xf084>;
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clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>;
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};
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