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Add Device Tree binding documentation for the ESWIN PCIe Root Complex. The Root Complex is based on Synopsys Designware PCIe IP. Signed-off-by: Yu Ning <ningyu@eswincomputing.com> Signed-off-by: Yanghui Ou <ouyanghui@eswincomputing.com> Signed-off-by: Senchuan Zhang <zhangsenchuan@eswincomputing.com> [mani: Renamed 'EIC7700' to 'ESWIN'] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: add driver tag in subject] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260227111732.1979-1-zhangsenchuan@eswincomputing.com
167 lines
3.7 KiB
YAML
167 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ESWIN PCIe Root Complex
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maintainers:
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- Yu Ning <ningyu@eswincomputing.com>
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- Senchuan Zhang <zhangsenchuan@eswincomputing.com>
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- Yanghui Ou <ouyanghui@eswincomputing.com>
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description:
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ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP.
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properties:
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compatible:
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const: eswin,eic7700-pcie
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: elbi
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ranges:
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maxItems: 3
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'#interrupt-cells':
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const: 1
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interrupt-names:
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items:
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- const: msi
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- const: inta
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- const: intb
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- const: intc
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- const: intd
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interrupt-map:
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maxItems: 4
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: mstr
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- const: dbi
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- const: phy_reg
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- const: aux
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: dbi
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- const: pwr
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patternProperties:
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"^pcie@":
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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num-lanes:
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maximum: 4
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: perst
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required:
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- reg
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- ranges
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- num-lanes
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- resets
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- reset-names
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- ranges
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- interrupts
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- interrupt-names
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- interrupt-map-mask
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- interrupt-map
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- '#interrupt-cells'
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- clocks
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- clock-names
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- resets
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- reset-names
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@54000000 {
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compatible = "eswin,eic7700-pcie";
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reg = <0x0 0x54000000 0x0 0x4000000>,
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<0x0 0x40000000 0x0 0x800000>,
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<0x0 0x50000000 0x0 0x100000>;
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reg-names = "dbi", "config", "elbi";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>,
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<0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>,
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<0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>;
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bus-range = <0x00 0xff>;
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clocks = <&clock 144>,
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<&clock 145>,
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<&clock 146>,
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<&clock 147>;
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clock-names = "mstr", "dbi", "phy_reg", "aux";
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resets = <&reset 97>,
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<&reset 98>;
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reset-names = "dbi", "pwr";
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interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
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interrupt-names = "msi", "inta", "intb", "intc", "intd";
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interrupt-parent = <&plic>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>,
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<0x0 0x0 0x0 0x2 &plic 180>,
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<0x0 0x0 0x0 0x3 &plic 181>,
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<0x0 0x0 0x0 0x4 &plic 182>;
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device_type = "pci";
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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device_type = "pci";
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num-lanes = <4>;
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resets = <&reset 99>;
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reset-names = "perst";
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};
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};
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};
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