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36545c6a68
Add compatible string "amd,versal2-dma-1.0" to support AMD Versal Gen 2 platform. AMD Versal Gen 2 has 8 LPD DMA IPs in PS that can be used as general purpose DMAs which is designed to support memory to memory and memory to IO buffer transfer. Versal Gen 2 DMA IP has different interrupt register offset. Signed-off-by: Abin Joseph <abin.joseph@amd.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240808100024.317497-2-abin.joseph@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
91 lines
1.9 KiB
YAML
91 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP DMA Engine
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description: |
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The Xilinx ZynqMP DMA engine supports memory to memory transfers,
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memory to device and device to memory transfers. It also has flow
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control and rate control support for slave/peripheral dma access.
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maintainers:
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- Michael Tretter <m.tretter@pengutronix.de>
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- Harini Katakam <harini.katakam@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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allOf:
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- $ref: ../dma-controller.yaml#
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properties:
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"#dma-cells":
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const: 1
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compatible:
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enum:
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- amd,versal2-dma-1.0
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- xlnx,zynqmp-dma-1.0
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reg:
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description: memory map for gdma/adma module access
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maxItems: 1
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interrupts:
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description: DMA channel interrupt
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maxItems: 1
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clocks:
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description: input clocks
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: clk_main
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- const: clk_apb
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xlnx,bus-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 64
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- 128
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description: AXI bus width in bits
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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dma-coherent:
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description: present if dma operations are coherent
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- xlnx,bus-width
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
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fpd_dma_chan1: dma-controller@fd500000 {
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0xfd500000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 117 0x4>;
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#dma-cells = <1>;
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clock-names = "clk_main", "clk_apb";
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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xlnx,bus-width = <128>;
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dma-coherent;
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};
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