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19fb11d722
Add a required clock property as we can't access the device registers if
the AXI bus clock is not properly enabled.
Note this clock is a very fundamental one that is typically enabled
pretty early during boot. Independently of that, we should really rely on
it to be enabled.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Fixes: 96553a44e9 ("dt-bindings: iio: adc: add bindings doc for AXI ADC driver")
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240426-ad9467-new-features-v2-3-6361fc3ba1cc@analog.com
Cc: <Stable@ver.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
69 lines
1.5 KiB
YAML
69 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AXI ADC IP core
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maintainers:
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- Michael Hennerich <michael.hennerich@analog.com>
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description: |
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Analog Devices Generic AXI ADC IP core for interfacing an ADC device
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with a high speed serial (JESD204B/C) or source synchronous parallel
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interface (LVDS/CMOS).
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Usually, some other interface type (i.e SPI) is used as a control
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interface for the actual ADC, while this IP core will interface
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to the data-lines of the ADC and handle the streaming of data into
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memory via DMA.
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https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
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properties:
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compatible:
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enum:
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- adi,axi-adc-10.0.a
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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maxItems: 1
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dma-names:
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items:
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- const: rx
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adi,adc-dev:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A reference to a the actual ADC to which this FPGA ADC interfaces to.
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deprecated: true
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'#io-backend-cells':
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const: 0
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required:
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- compatible
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- dmas
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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axi-adc@44a00000 {
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compatible = "adi,axi-adc-10.0.a";
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reg = <0x44a00000 0x10000>;
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dmas = <&rx_dma 0>;
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dma-names = "rx";
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clocks = <&axi_clk>;
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#io-backend-cells = <0>;
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};
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...
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