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83d4e04431
Compared to the existing Allwinner H6 OPP scheme, the H616 uses a similar NVMEM based mechanism to determine the silicon revision, which is required to select the right frequency / voltage pair for the OPPs. However it limits the maximum frequency for some speed bins, also seems to not support all frequencies in all speed bins, which requires us to introduce the opp-supported-hw property. Add this property to the list of allowed properties, also drop the requirement for the revision specific opp-microvolt properties, since they might not be needed if using opp-supported-hw. Also use to opportunity to adjust some wording, and drop a sentence referring to the Linux driver and the OPP subsystem. Shorten the existing example and add another example, showcasing the opp-supported-hw property. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
135 lines
3.5 KiB
YAML
135 lines
3.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner H6 CPU OPP
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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description: |
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For some SoCs, the CPU frequency subset and voltage value of each
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OPP varies based on the silicon variant in use. Allwinner Process
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Voltage Scaling Tables define the voltage and frequency values based
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on the speedbin blown in the efuse combination.
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allOf:
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- $ref: opp-v2-base.yaml#
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properties:
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compatible:
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enum:
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- allwinner,sun50i-h6-operating-points
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- allwinner,sun50i-h616-operating-points
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nvmem-cells:
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description: |
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A phandle pointing to a nvmem-cells node representing the efuse
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register that has information about the speedbin that is used
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to select the right frequency/voltage value pair. Please refer
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to the nvmem-cells bindings in
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Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the
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examples below.
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opp-shared: true
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required:
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- compatible
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- nvmem-cells
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patternProperties:
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"^opp-[0-9]+$":
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type: object
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properties:
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opp-hz: true
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clock-latency-ns: true
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opp-microvolt: true
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opp-supported-hw:
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maxItems: 1
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description:
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A single 32 bit bitmap value, representing compatible HW, one
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bit per speed bin index.
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patternProperties:
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"^opp-microvolt-speed[0-9]$": true
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required:
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- opp-hz
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unevaluatedProperties: false
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additionalProperties: false
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examples:
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- |
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cpu_opp_table: opp-table {
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compatible = "allwinner,sun50i-h6-operating-points";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-480000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp-1080000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1080000000>;
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opp-microvolt-speed0 = <1060000>;
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opp-microvolt-speed1 = <880000>;
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opp-microvolt-speed2 = <840000>;
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};
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opp-1488000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt-speed0 = <1160000>;
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opp-microvolt-speed1 = <1000000>;
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opp-microvolt-speed2 = <960000>;
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};
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};
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- |
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opp-table {
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compatible = "allwinner,sun50i-h616-operating-points";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-480000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <900000>;
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opp-supported-hw = <0x1f>;
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};
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opp-792000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <792000000>;
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opp-microvolt-speed1 = <900000>;
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opp-microvolt-speed4 = <940000>;
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opp-supported-hw = <0x12>;
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};
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opp-1512000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1512000000>;
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opp-microvolt = <1100000>;
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opp-supported-hw = <0x0a>;
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};
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};
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...
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