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>From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add a rockchip specific property to enable/disable the rxX_cmn_refclk_mode per lane. (Since this PHY supports bifurcation.) Signed-off-by: Niklas Cassel <cassel@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240412125818.17052-2-cassel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
114 lines
2.5 KiB
YAML
114 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip PCIe v3 phy
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,rk3568-pcie3-phy
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- rockchip,rk3588-pcie3-phy
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 3
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clock-names:
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minItems: 1
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maxItems: 3
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data-lanes:
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description: which lanes (by position) should be mapped to which
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controller (value). 0 means lane disabled, higher value means used.
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(controller-number +1 )
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 16
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items:
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minimum: 0
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maximum: 16
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"#phy-cells":
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const: 0
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resets:
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maxItems: 1
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reset-names:
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const: phy
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rockchip,phy-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the syscon managing the phy "general register files"
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rockchip,pipe-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the syscon managing the pipe "general register files"
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rockchip,rx-common-refclk-mode:
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description: which lanes (by position) should be configured to run in
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RX common reference clock mode. 0 means disabled, 1 means enabled.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 16
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items:
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minimum: 0
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maximum: 1
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required:
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- compatible
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- reg
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- rockchip,phy-grf
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- "#phy-cells"
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- rockchip,rk3588-pcie3-phy
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: pclk
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else:
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properties:
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clocks:
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minItems: 3
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clock-names:
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items:
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- const: refclk_m
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- const: refclk_n
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- const: pclk
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3568-cru.h>
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pcie30phy: phy@fe8c0000 {
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compatible = "rockchip,rk3568-pcie3-phy";
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reg = <0xfe8c0000 0x20000>;
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#phy-cells = <0>;
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clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
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<&pmucru CLK_PCIE30PHY_REF_N>,
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<&cru PCLK_PCIE30PHY>;
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clock-names = "refclk_m", "refclk_n", "pclk";
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resets = <&cru SRST_PCIE30PHY>;
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reset-names = "phy";
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rockchip,phy-grf = <&pcie30_phy_grf>;
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};
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