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f9d48a88eb
[WHY] Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM pipesplit is used, pixels on the left edge of ODM slices need one extra pixel from the right edge of the previous slice to calculate the correct chroma value. Without this change, the chroma value is slightly different than expected. This is usually imperceptible visually, but it impacts test pattern CRCs for compliance test automation. [HOW] Update logic to use the register for adding extra left edge pixel for YCbCr422/420 ODM cases. Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
75 lines
2.7 KiB
C
75 lines
2.7 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dcn201_opp.h"
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#include "reg_helper.h"
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#define REG(reg) \
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(oppn201->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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oppn201->opp_shift->field_name, oppn201->opp_mask->field_name
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#define CTX \
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oppn201->base.ctx
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/*****************************************/
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/* Constructor, Destructor */
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/*****************************************/
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static struct opp_funcs dcn201_opp_funcs = {
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.opp_set_dyn_expansion = opp1_set_dyn_expansion,
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.opp_program_fmt = opp1_program_fmt,
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.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
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.opp_program_stereo = opp1_program_stereo,
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.opp_pipe_clock_control = opp1_pipe_clock_control,
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.opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator,
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.opp_program_dpg_dimensions = opp2_program_dpg_dimensions,
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.dpg_is_blanked = opp2_dpg_is_blanked,
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.dpg_is_pending = opp2_dpg_is_pending,
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.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
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.opp_destroy = opp1_destroy,
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.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,
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.opp_get_left_edge_extra_pixel_count = opp2_get_left_edge_extra_pixel_count,
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};
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void dcn201_opp_construct(struct dcn201_opp *oppn201,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn201_opp_registers *regs,
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const struct dcn201_opp_shift *opp_shift,
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const struct dcn201_opp_mask *opp_mask)
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{
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oppn201->base.ctx = ctx;
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oppn201->base.inst = inst;
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oppn201->base.funcs = &dcn201_opp_funcs;
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oppn201->regs = regs;
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oppn201->opp_shift = opp_shift;
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oppn201->opp_mask = opp_mask;
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}
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