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a262cc8d55
Enable Xe2+ PES disaggregation (for OAG) to retrieve disaggregated metrics when disaggregated data is needed. Userspace can select whether to receive aggregated or disaggregated metrics via the particular OA configuration it uses (programmed via DRM_XE_OBSERVATION_OP_ADD_CONFIG). Bspec: 61101 Fixes:e936f885f1("drm/xe/oa/uapi: Expose OA stream fd") Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240909165933.2638765-1-ashutosh.dixit@intel.com Cc: stable@vger.kernel.org (cherry picked from commitfb2551a0e9) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
102 lines
3.9 KiB
C
102 lines
3.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __XE_OA_REGS__
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#define __XE_OA_REGS__
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#define RPM_CONFIG1 XE_REG(0xd04)
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#define GT_NOA_ENABLE REG_BIT(9)
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#define EU_PERF_CNTL0 XE_REG(0xe458)
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#define EU_PERF_CNTL4 XE_REG(0xe45c)
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#define EU_PERF_CNTL1 XE_REG(0xe558)
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#define EU_PERF_CNTL5 XE_REG(0xe55c)
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#define EU_PERF_CNTL2 XE_REG(0xe658)
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#define EU_PERF_CNTL6 XE_REG(0xe65c)
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#define EU_PERF_CNTL3 XE_REG(0xe758)
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#define OA_TLB_INV_CR XE_REG(0xceec)
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/* OAR unit */
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#define OAR_OACONTROL XE_REG(0x2960)
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#define OAR_OACONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
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#define OAR_OACONTROL_COUNTER_ENABLE REG_BIT(0)
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#define OACTXCONTROL(base) XE_REG((base) + 0x360)
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#define OAR_OASTATUS XE_REG(0x2968)
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#define OA_COUNTER_RESUME REG_BIT(0)
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/* OAG unit */
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#define OAG_OAGLBCTXCTRL XE_REG(0x2b28)
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#define OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK REG_GENMASK(7, 2)
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#define OAG_OAGLBCTXCTRL_TIMER_ENABLE REG_BIT(1)
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#define OAG_OAGLBCTXCTRL_COUNTER_RESUME REG_BIT(0)
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#define OAG_OAHEADPTR XE_REG(0xdb00)
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#define OAG_OAHEADPTR_MASK REG_GENMASK(31, 6)
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#define OAG_OATAILPTR XE_REG(0xdb04)
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#define OAG_OATAILPTR_MASK REG_GENMASK(31, 6)
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#define OAG_OABUFFER XE_REG(0xdb08)
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#define OABUFFER_SIZE_MASK REG_GENMASK(5, 3)
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#define OABUFFER_SIZE_128K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 0)
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#define OABUFFER_SIZE_256K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 1)
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#define OABUFFER_SIZE_512K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 2)
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#define OABUFFER_SIZE_1M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 3)
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#define OABUFFER_SIZE_2M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 4)
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#define OABUFFER_SIZE_4M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 5)
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#define OABUFFER_SIZE_8M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 6)
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#define OABUFFER_SIZE_16M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 7)
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#define OAG_OABUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
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#define OAG_OACONTROL XE_REG(0xdaf4)
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#define OAG_OACONTROL_OA_PES_DISAG_EN REG_GENMASK(27, 22)
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#define OAG_OACONTROL_OA_CCS_SELECT_MASK REG_GENMASK(18, 16)
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#define OAG_OACONTROL_OA_COUNTER_SEL_MASK REG_GENMASK(4, 2)
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#define OAG_OACONTROL_OA_COUNTER_ENABLE REG_BIT(0)
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/* Common to all OA units */
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#define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9)
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#define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8)
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#define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED)
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#define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14)
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#define OAG_OA_DEBUG_START_TRIGGER_SCOPE_CONTROL REG_BIT(13)
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#define OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL REG_BIT(8)
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#define OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL REG_BIT(7)
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#define OAG_OA_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6)
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#define OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5)
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#define OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1)
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#define OAG_OASTATUS XE_REG(0xdafc)
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#define OASTATUS_MMIO_TRG_Q_FULL REG_BIT(6)
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#define OASTATUS_COUNTER_OVERFLOW REG_BIT(2)
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#define OASTATUS_BUFFER_OVERFLOW REG_BIT(1)
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#define OASTATUS_REPORT_LOST REG_BIT(0)
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#define OAG_MMIOTRIGGER XE_REG(0xdb1c)
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/* OAC unit */
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#define OAC_OACONTROL XE_REG(0x15114)
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/* OAM unit */
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#define OAM_HEAD_POINTER_OFFSET (0x1a0)
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#define OAM_TAIL_POINTER_OFFSET (0x1a4)
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#define OAM_BUFFER_OFFSET (0x1a8)
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#define OAM_CONTEXT_CONTROL_OFFSET (0x1bc)
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#define OAM_CONTROL_OFFSET (0x194)
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#define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
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#define OAM_DEBUG_OFFSET (0x198)
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#define OAM_STATUS_OFFSET (0x19c)
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#define OAM_MMIO_TRG_OFFSET (0x1d0)
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#define OAM_HEAD_POINTER(base) XE_REG((base) + OAM_HEAD_POINTER_OFFSET)
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#define OAM_TAIL_POINTER(base) XE_REG((base) + OAM_TAIL_POINTER_OFFSET)
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#define OAM_BUFFER(base) XE_REG((base) + OAM_BUFFER_OFFSET)
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#define OAM_CONTEXT_CONTROL(base) XE_REG((base) + OAM_CONTEXT_CONTROL_OFFSET)
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#define OAM_CONTROL(base) XE_REG((base) + OAM_CONTROL_OFFSET)
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#define OAM_DEBUG(base) XE_REG((base) + OAM_DEBUG_OFFSET)
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#define OAM_STATUS(base) XE_REG((base) + OAM_STATUS_OFFSET)
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#define OAM_MMIO_TRG(base) XE_REG((base) + OAM_MMIO_TRG_OFFSET)
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#endif
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