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1505bc70f8
It would appear that all of the selftests are using the same exact layout for the GIC frames. Fold this back into the library implementation to avoid defining magic values all over the selftests. This is an extension of Colton's change, ripping out parameterization of from the library internals in addition to the public interfaces. Co-developed-by: Colton Lewis <coltonlewis@google.com> Signed-off-by: Colton Lewis <coltonlewis@google.com> Signed-off-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20240422200158.2606761-15-oliver.upton@linux.dev Signed-off-by: Marc Zyngier <maz@kernel.org>
158 lines
3.1 KiB
C
158 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Generic Interrupt Controller (GIC) support
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*/
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#include <errno.h>
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#include <linux/bits.h>
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#include <linux/sizes.h>
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#include "kvm_util.h"
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#include <gic.h>
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#include "gic_private.h"
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#include "processor.h"
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#include "spinlock.h"
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static const struct gic_common_ops *gic_common_ops;
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static struct spinlock gic_lock;
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static void gic_cpu_init(unsigned int cpu)
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{
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gic_common_ops->gic_cpu_init(cpu);
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}
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static void gic_dist_init(enum gic_type type, unsigned int nr_cpus)
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{
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const struct gic_common_ops *gic_ops = NULL;
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spin_lock(&gic_lock);
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/* Distributor initialization is needed only once per VM */
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if (gic_common_ops) {
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spin_unlock(&gic_lock);
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return;
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}
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if (type == GIC_V3)
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gic_ops = &gicv3_ops;
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GUEST_ASSERT(gic_ops);
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gic_ops->gic_init(nr_cpus);
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gic_common_ops = gic_ops;
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/* Make sure that the initialized data is visible to all the vCPUs */
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dsb(sy);
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spin_unlock(&gic_lock);
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}
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void gic_init(enum gic_type type, unsigned int nr_cpus)
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{
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uint32_t cpu = guest_get_vcpuid();
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GUEST_ASSERT(type < GIC_TYPE_MAX);
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GUEST_ASSERT(nr_cpus);
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gic_dist_init(type, nr_cpus);
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gic_cpu_init(cpu);
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}
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void gic_irq_enable(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_enable(intid);
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}
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void gic_irq_disable(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_disable(intid);
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}
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unsigned int gic_get_and_ack_irq(void)
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{
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uint64_t irqstat;
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unsigned int intid;
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GUEST_ASSERT(gic_common_ops);
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irqstat = gic_common_ops->gic_read_iar();
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intid = irqstat & GENMASK(23, 0);
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return intid;
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}
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void gic_set_eoi(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_write_eoir(intid);
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}
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void gic_set_dir(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_write_dir(intid);
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}
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void gic_set_eoi_split(bool split)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_set_eoi_split(split);
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}
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void gic_set_priority_mask(uint64_t pmr)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_set_priority_mask(pmr);
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}
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void gic_set_priority(unsigned int intid, unsigned int prio)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_set_priority(intid, prio);
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}
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void gic_irq_set_active(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_active(intid);
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}
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void gic_irq_clear_active(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_clear_active(intid);
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}
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bool gic_irq_get_active(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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return gic_common_ops->gic_irq_get_active(intid);
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}
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void gic_irq_set_pending(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_pending(intid);
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}
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void gic_irq_clear_pending(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_clear_pending(intid);
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}
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bool gic_irq_get_pending(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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return gic_common_ops->gic_irq_get_pending(intid);
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}
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void gic_irq_set_config(unsigned int intid, bool is_edge)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_config(intid, is_edge);
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}
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