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Convert the direct IO accesses to properly defined registers. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20260314-register-v9-9-86805b2f7e9d@nvidia.com [ Fix up kernel import style. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
199 lines
4.6 KiB
Rust
199 lines
4.6 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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//! Rust PCI driver sample (based on QEMU's `pci-testdev`).
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//!
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//! To make this driver probe, QEMU must be run with `-device pci-testdev`.
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use kernel::{
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device::{
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Bound,
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Core, //
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},
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devres::Devres,
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io::{
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register,
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register::Array,
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Io, //
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},
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num::Bounded,
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pci,
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prelude::*,
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sync::aref::ARef, //
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};
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mod regs {
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use super::*;
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register! {
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pub(super) TEST(u8) @ 0x0 {
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7:0 index => TestIndex;
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}
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pub(super) OFFSET(u32) @ 0x4 {
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31:0 offset;
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}
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pub(super) DATA(u8) @ 0x8 {
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7:0 data;
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}
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pub(super) COUNT(u32) @ 0xC {
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31:0 count;
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}
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}
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pub(super) const END: usize = 0x10;
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}
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type Bar0 = pci::Bar<{ regs::END }>;
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#[derive(Copy, Clone, Debug)]
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struct TestIndex(u8);
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impl From<Bounded<u8, 8>> for TestIndex {
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fn from(value: Bounded<u8, 8>) -> Self {
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Self(value.into())
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}
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}
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impl From<TestIndex> for Bounded<u8, 8> {
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fn from(value: TestIndex) -> Self {
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value.0.into()
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}
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}
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impl TestIndex {
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const NO_EVENTFD: Self = Self(0);
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}
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#[pin_data(PinnedDrop)]
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struct SampleDriver {
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pdev: ARef<pci::Device>,
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#[pin]
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bar: Devres<Bar0>,
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index: TestIndex,
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}
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kernel::pci_device_table!(
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PCI_TABLE,
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MODULE_PCI_TABLE,
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<SampleDriver as pci::Driver>::IdInfo,
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[(
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pci::DeviceId::from_id(pci::Vendor::REDHAT, 0x5),
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TestIndex::NO_EVENTFD
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)]
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);
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impl SampleDriver {
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fn testdev(index: &TestIndex, bar: &Bar0) -> Result<u32> {
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// Select the test.
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bar.write_reg(regs::TEST::zeroed().with_index(*index));
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let offset = bar.read(regs::OFFSET).into_raw() as usize;
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let data = bar.read(regs::DATA).into();
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// Write `data` to `offset` to increase `count` by one.
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//
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// Note that we need `try_write8`, since `offset` can't be checked at compile-time.
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bar.try_write8(data, offset)?;
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Ok(bar.read(regs::COUNT).into())
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}
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fn config_space(pdev: &pci::Device<Bound>) {
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let config = pdev.config_space();
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// Some PCI configuration space registers.
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register! {
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VENDOR_ID(u16) @ 0x0 {
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15:0 vendor_id;
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}
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REVISION_ID(u8) @ 0x8 {
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7:0 revision_id;
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}
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BAR(u32)[6] @ 0x10 {
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31:0 value;
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}
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}
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dev_info!(
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pdev,
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"pci-testdev config space read8 rev ID: {:x}\n",
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config.read(REVISION_ID).revision_id()
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);
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dev_info!(
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pdev,
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"pci-testdev config space read16 vendor ID: {:x}\n",
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config.read(VENDOR_ID).vendor_id()
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);
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dev_info!(
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pdev,
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"pci-testdev config space read32 BAR 0: {:x}\n",
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config.read(BAR::at(0)).value()
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);
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}
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}
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impl pci::Driver for SampleDriver {
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type IdInfo = TestIndex;
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const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE;
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fn probe(pdev: &pci::Device<Core>, info: &Self::IdInfo) -> impl PinInit<Self, Error> {
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pin_init::pin_init_scope(move || {
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let vendor = pdev.vendor_id();
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dev_dbg!(
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pdev,
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"Probe Rust PCI driver sample (PCI ID: {}, 0x{:x}).\n",
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vendor,
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pdev.device_id()
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);
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pdev.enable_device_mem()?;
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pdev.set_master();
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Ok(try_pin_init!(Self {
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bar <- pdev.iomap_region_sized::<{ regs::END }>(0, c"rust_driver_pci"),
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index: *info,
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_: {
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let bar = bar.access(pdev.as_ref())?;
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dev_info!(
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pdev,
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"pci-testdev data-match count: {}\n",
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Self::testdev(info, bar)?
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);
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Self::config_space(pdev);
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},
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pdev: pdev.into(),
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}))
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})
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}
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fn unbind(pdev: &pci::Device<Core>, this: Pin<&Self>) {
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if let Ok(bar) = this.bar.access(pdev.as_ref()) {
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// Reset pci-testdev by writing a new test index.
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bar.write_reg(regs::TEST::zeroed().with_index(this.index));
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}
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}
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}
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#[pinned_drop]
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impl PinnedDrop for SampleDriver {
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fn drop(self: Pin<&mut Self>) {
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dev_dbg!(self.pdev, "Remove Rust PCI driver sample.\n");
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}
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}
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kernel::module_pci_driver! {
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type: SampleDriver,
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name: "rust_driver_pci",
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authors: ["Danilo Krummrich"],
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description: "Rust PCI driver",
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license: "GPL v2",
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}
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