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T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock and two reset controls. Add a device tree binding to it. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260129023922.1527729-5-zhengxingda@iscas.ac.cn
121 lines
2.6 KiB
YAML
121 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: T-Head TH1520 DesignWare HDMI TX Encoder
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maintainers:
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- Icenowy Zheng <uwu@icenowy.me>
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description:
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The HDMI transmitter is a Synopsys DesignWare HDMI TX controller
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paired with a DesignWare HDMI Gen2 TX PHY.
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allOf:
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- $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
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properties:
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compatible:
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enum:
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- thead,th1520-dw-hdmi
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reg-io-width:
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const: 4
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: iahb
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- const: isfr
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- const: cec
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- const: pix
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resets:
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items:
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- description: Main reset
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- description: Configuration APB reset
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reset-names:
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items:
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- const: main
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- const: apb
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input port connected to DC8200 DPU "DP" output
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: HDMI output port
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- reg-io-width
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- clocks
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- clock-names
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- resets
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- reset-names
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- interrupts
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- ports
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/thead,th1520-clk-ap.h>
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#include <dt-bindings/reset/thead,th1520-reset.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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hdmi@ffef540000 {
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compatible = "thead,th1520-dw-hdmi";
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reg = <0xff 0xef540000 0x0 0x40000>;
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reg-io-width = <4>;
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interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_vo CLK_HDMI_PCLK>,
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<&clk_vo CLK_HDMI_SFR>,
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<&clk_vo CLK_HDMI_CEC>,
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<&clk_vo CLK_HDMI_PIXCLK>;
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clock-names = "iahb", "isfr", "cec", "pix";
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resets = <&rst_vo TH1520_RESET_ID_HDMI>,
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<&rst_vo TH1520_RESET_ID_HDMI_APB>;
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reset-names = "main", "apb";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi_in: endpoint {
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remote-endpoint = <&dpu_out_dp1>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_out_conn: endpoint {
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remote-endpoint = <&hdmi_conn_in>;
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};
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};
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};
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};
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};
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