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The DisplayPort found on RK3576 is very similar to that of RK3588, but work in dual pixel mode. And itself does not depend on the I2S clock or the SPDIF clock when transmit audio. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260206010421.443605-2-andyshrk@163.com
171 lines
3.8 KiB
YAML
171 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip DW DisplayPort Transmitter
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maintainers:
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- Andy Yan <andy.yan@rock-chips.com>
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description: |
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The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller
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which is compliant with the DisplayPort Specification Version 1.4 with the
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following features:
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* DisplayPort 1.4a
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* Main Link: 1/2/4 lanes
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* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
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* AUX channel 1Mbps
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* Single Stream Transport(SST)
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* Multistream Transport (MST)
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* Type-C support (alternate mode)
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* HDCP 2.2, HDCP 1.3
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* Supports up to 8/10 bits per color component
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* Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0
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* Pixel clock up to 594MHz
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* I2S, SPDIF audio interface
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properties:
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compatible:
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enum:
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- rockchip,rk3576-dp
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- rockchip,rk3588-dp
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 3
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items:
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- description: Peripheral/APB bus clock
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- description: DisplayPort AUX clock
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- description: HDCP clock
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- description: I2S interface clock
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- description: SPDIF interfce clock
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clock-names:
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minItems: 3
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items:
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- const: apb
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- const: aux
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- const: hdcp
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- const: i2s
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- const: spdif
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phys:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for RGB/YUV input.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for DP output.
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required:
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- port@0
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- port@1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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"#sound-dai-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- phys
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- ports
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- resets
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allOf:
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- $ref: /schemas/sound/dai-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,rk3588-dp
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then:
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properties:
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clocks:
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minItems: 5
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clock-names:
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minItems: 5
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else:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dp@fde50000 {
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compatible = "rockchip,rk3588-dp";
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reg = <0x0 0xfde50000 0x0 0x4000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
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<&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
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<&cru MCLK_SPDIF2_DP0>;
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clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
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assigned-clocks = <&cru CLK_AUX16M_0>;
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assigned-clock-rates = <16000000>;
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resets = <&cru SRST_DP0>;
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phys = <&usbdp_phy0 PHY_TYPE_DP>;
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power-domains = <&power RK3588_PD_VO0>;
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#sound-dai-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dp0_in_vp2: endpoint {
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remote-endpoint = <&vp2_out_dp0>;
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};
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};
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port@1 {
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reg = <1>;
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dp0_out_con0: endpoint {
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remote-endpoint = <&dp_con0_in>;
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};
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};
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};
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};
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};
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