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7376ba2db1
Add "adi,low-cmode-impedance" boolean property which, when present, configures the PHY for the lowest common-mode impedance on the receive pair for 100BASE-TX operation by clearing the B_100_ZPTM_EN_DIMRX bit. This is suited for capacitive coupled applications and other applications where there may be a path for high common-mode noise to reach the PHY. If this value is not present, the value of the bit by default is 1, which is normal termination (zero-power termination) mode. Signed-off-by: Osose Itua <osose.itua@savoirfairelinux.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260107221913.1334157-2-osose.itua@savoirfairelinux.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
99 lines
2.7 KiB
YAML
99 lines
2.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0+
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/adi,adin.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices ADIN1200/ADIN1300 PHY
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maintainers:
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- Marcelo Schmitt <marcelo.schmitt@analog.com>
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description: |
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Bindings for Analog Devices Industrial Ethernet PHYs
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allOf:
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- $ref: ethernet-phy.yaml#
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properties:
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adi,rx-internal-delay-ps:
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description: |
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RGMII RX Clock Delay used only when PHY operates in RGMII mode with
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internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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enum: [ 1600, 1800, 2000, 2200, 2400 ]
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default: 2000
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adi,tx-internal-delay-ps:
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description: |
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RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
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enum: [ 1600, 1800, 2000, 2200, 2400 ]
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default: 2000
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adi,fifo-depth-bits:
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description: |
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When operating in RMII mode, this option configures the FIFO depth.
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enum: [ 4, 8, 12, 16, 20, 24 ]
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default: 8
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adi,phy-output-clock:
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description: |
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Select clock output on GP_CLK pin. Two clocks are available:
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A 25MHz reference and a free-running 125MHz.
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The phy can alternatively automatically switch between the reference and
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the 125MHz clocks based on its internal state.
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- 25mhz-reference
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- 125mhz-free-running
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- adaptive-free-running
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adi,phy-output-reference-clock:
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description: Enable 25MHz reference clock output on CLK25_REF pin.
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type: boolean
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adi,low-cmode-impedance:
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description: |
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Configure PHY for the lowest common-mode impedance on the receive pair
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for 100BASE-TX. This is suited for capacitive coupled applications and
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other applications where there may be a path for high common-mode noise
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to reach the PHY.
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If not present, by default the PHY is configured for normal termination
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(zero-power termination) mode.
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Note: There is a trade-off of 12 mW increased power consumption with
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the lowest common-mode impedance setting, but in all cases the
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differential impedance is 100 ohms.
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type: boolean
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unevaluatedProperties: false
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examples:
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- |
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii-id";
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ethernet-phy@0 {
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reg = <0>;
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adi,rx-internal-delay-ps = <1800>;
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adi,tx-internal-delay-ps = <2200>;
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};
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};
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- |
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rmii";
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ethernet-phy@1 {
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reg = <1>;
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adi,fifo-depth-bits = <16>;
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};
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};
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