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For gfxV9, due to a hardware bug ("based on the comments in the code
here [1]"), the control stack of a user-mode compute queue must be
allocated immediately after the page boundary of its regular MQD buffer.
To handle this, we allocate an enlarged MQD buffer where the first page
is used as the MQD and the remaining pages store the control stack.
Although these regions share the same BO, they require different memory
types: the MQD must be UC (uncached), while the control stack must be
NC (non-coherent), matching the behavior when the control stack is
allocated in user space.
This logic works correctly on systems where the CPU page size matches
the GPU page size (4K). However, the current implementation aligns both
the MQD and the control stack to the CPU PAGE_SIZE. On systems with a
larger CPU page size, the entire first CPU page is marked UC—even though
that page may contain multiple GPU pages. The GPU treats the second 4K
GPU page inside that CPU page as part of the control stack, but it is
incorrectly mapped as UC.
This patch fixes the issue by aligning both the MQD and control stack
sizes to the GPU page size (4K). The first 4K page is correctly marked
as UC for the MQD, and the remaining GPU pages are marked NC for the
control stack. This ensures proper memory type assignment on systems
with larger CPU page sizes.
[1]: https://elixir.bootlin.com/linux/v6.18/source/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c#L118
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Donet Tom <donettom@linux.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 998d678141)
74 lines
2.8 KiB
C
74 lines
2.8 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_GART_H__
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#define __AMDGPU_GART_H__
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#include <linux/types.h>
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/*
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* GART structures, functions & helpers
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*/
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struct amdgpu_device;
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struct amdgpu_bo;
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#define AMDGPU_GPU_PAGE_SIZE 4096
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#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
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#define AMDGPU_GPU_PAGE_SHIFT 12
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#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
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#define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
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struct amdgpu_gart {
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struct amdgpu_bo *bo;
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/* CPU kmapped address of gart table */
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void *ptr;
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unsigned num_gpu_pages;
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unsigned num_cpu_pages;
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unsigned table_size;
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/* Asic default pte flags */
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uint64_t gart_pte_flags;
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};
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int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
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void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
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void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
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int amdgpu_gart_init(struct amdgpu_device *adev);
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void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
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void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
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int pages);
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void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
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int pages, dma_addr_t *dma_addr, uint64_t flags,
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void *dst);
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void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset,
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int pages, dma_addr_t *dma_addr, uint64_t flags);
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void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
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int pages, dma_addr_t *dma_addr, uint64_t flags);
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void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
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uint64_t start_page, uint64_t num_pages,
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uint64_t flags, void *dst);
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void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
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#endif
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