Charlene Liu a1fc2837f4 drm/amd/display: update dcn351 used clock offset ...

[why]
hw register offset delta

Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2024-12-10 10:37:16 -05:00

..

dcn35_clk_mgr.c

drm/amd/display: update dcn351 used clock offset

2024-12-10 10:37:16 -05:00

dcn35_clk_mgr.h

drm/amd/display: update dcn351 used clock offset

2024-12-10 10:37:16 -05:00

dcn35_smu.c

drm/amd/display: Send message to notify the DPIA host router bandwidth

2024-06-14 16:18:55 -04:00

dcn35_smu.h

drm/amd/display: correct dcn351 dpm clk table based on pmfw_drv_if

2024-12-10 10:26:49 -05:00

dcn351_clk_mgr.c

drm/amd/display: update dcn351 used clock offset

2024-12-10 10:37:16 -05:00