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50709e6343
In MDP3, a pipe is used to represent a data path which
consisting of different components and MUTEX, as shown in
the following diagram:
+----------------------------+
| MUTEX [*1] |
+----------------------------+
S ^ S ^ S ^ S ^ S ^
| | | | | | | | | |
| | | | | | | | | |
+--------------+ | | | | | | | | +-------------+
| +--------------+ | | | | | | +-------------+ |
| | +------+ | | | | +------+ | |
| | | +------+ | | +------+ | | |
| | | | | | | | | |
| | | | | | | | | |
v E v E v E v E v E
+-------+ +-----+ +-------+ +-----+ +-------+
B>--->| RDMA0 |>-->| PQ |>-->| RSZ0 |>-->| PQ |>-->| WROT0 |>-->B
+-------+ +-----+ +-------+ +-----+ +-------+
[*1] MUTEX is SOF/EOF signal controller
[*2] S = Start of frame (SOF)
[*3] E = End of frame (EOF)
[*4] B = frame buffer
More pipes will be introduced in future chips for applications such as
higher frame rate frequency, which should integrate and reorder related
information into specific chip config file.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
452 lines
11 KiB
C
452 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#include "mtk-mdp3-cfg.h"
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#include "mtk-mdp3-core.h"
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#include "mtk-mdp3-comp.h"
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#include "mtk-mdp3-regs.h"
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enum mt8183_mdp_comp_id {
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/* ISP */
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MT8183_MDP_COMP_WPEI = 0,
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MT8183_MDP_COMP_WPEO, /* 1 */
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MT8183_MDP_COMP_WPEI2, /* 2 */
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MT8183_MDP_COMP_WPEO2, /* 3 */
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MT8183_MDP_COMP_ISP_IMGI, /* 4 */
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MT8183_MDP_COMP_ISP_IMGO, /* 5 */
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MT8183_MDP_COMP_ISP_IMG2O, /* 6 */
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/* IPU */
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MT8183_MDP_COMP_IPUI, /* 7 */
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MT8183_MDP_COMP_IPUO, /* 8 */
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/* MDP */
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MT8183_MDP_COMP_CAMIN, /* 9 */
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MT8183_MDP_COMP_CAMIN2, /* 10 */
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MT8183_MDP_COMP_RDMA0, /* 11 */
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MT8183_MDP_COMP_AAL0, /* 12 */
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MT8183_MDP_COMP_CCORR0, /* 13 */
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MT8183_MDP_COMP_RSZ0, /* 14 */
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MT8183_MDP_COMP_RSZ1, /* 15 */
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MT8183_MDP_COMP_TDSHP0, /* 16 */
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MT8183_MDP_COMP_COLOR0, /* 17 */
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MT8183_MDP_COMP_PATH0_SOUT, /* 18 */
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MT8183_MDP_COMP_PATH1_SOUT, /* 19 */
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MT8183_MDP_COMP_WROT0, /* 20 */
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MT8183_MDP_COMP_WDMA, /* 21 */
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/* Dummy Engine */
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MT8183_MDP_COMP_RDMA1, /* 22 */
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MT8183_MDP_COMP_RSZ2, /* 23 */
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MT8183_MDP_COMP_TDSHP1, /* 24 */
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MT8183_MDP_COMP_WROT1, /* 25 */
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};
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static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = {
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[MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" },
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[MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8183-disp-mutex" },
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[MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" }
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};
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static const struct mdp_platform_config mt8183_plat_cfg = {
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.rdma_support_10bit = true,
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.rdma_rsz1_sram_sharing = true,
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.rdma_upsample_repeat_only = true,
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.rsz_disable_dcm_small_sample = false,
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.wrot_filter_constraint = false,
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};
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static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0,
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[MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0,
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[MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1,
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[MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0,
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[MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0,
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[MDP_COMP_WDMA] = MUTEX_MOD_IDX_MDP_WDMA,
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[MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0,
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[MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0,
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};
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static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
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[MDP_COMP_WPEI] = {
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{MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI},
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{0, 0, 0}
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},
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[MDP_COMP_WPEO] = {
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{MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO},
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{0, 0, 0}
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},
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[MDP_COMP_WPEI2] = {
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{MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2},
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{0, 0, 0}
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},
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[MDP_COMP_WPEO2] = {
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{MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2},
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{0, 0, 0}
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},
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[MDP_COMP_ISP_IMGI] = {
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{MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI},
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{0, 0, 4}
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},
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[MDP_COMP_ISP_IMGO] = {
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{MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO},
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{0, 0, 4}
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},
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[MDP_COMP_ISP_IMG2O] = {
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{MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O},
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{0, 0, 0}
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},
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[MDP_COMP_CAMIN] = {
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{MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN},
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{2, 2, 1}
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},
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[MDP_COMP_CAMIN2] = {
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{MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2},
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{2, 4, 1}
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},
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[MDP_COMP_RDMA0] = {
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{MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0},
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{2, 0, 0}
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},
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[MDP_COMP_CCORR0] = {
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{MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0},
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{1, 0, 0}
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},
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[MDP_COMP_RSZ0] = {
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{MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0},
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{1, 0, 0}
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},
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[MDP_COMP_RSZ1] = {
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{MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1},
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{1, 0, 0}
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},
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[MDP_COMP_TDSHP0] = {
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{MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0},
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{0, 0, 0}
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},
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[MDP_COMP_PATH0_SOUT] = {
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{MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT},
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{0, 0, 0}
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},
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[MDP_COMP_PATH1_SOUT] = {
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{MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT},
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{0, 0, 0}
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},
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[MDP_COMP_WROT0] = {
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{MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0},
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{1, 0, 0}
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},
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[MDP_COMP_WDMA] = {
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{MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA},
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{1, 0, 0}
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},
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};
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static const struct of_device_id mt8183_sub_comp_dt_ids[] = {
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{
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.compatible = "mediatek,mt8183-mdp3-wdma",
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.data = (void *)MDP_COMP_TYPE_PATH,
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}, {
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.compatible = "mediatek,mt8183-mdp3-wrot",
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.data = (void *)MDP_COMP_TYPE_PATH,
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},
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{}
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};
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/*
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* All 10-bit related formats are not added in the basic format list,
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* please add the corresponding format settings before use.
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*/
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static const struct mdp_format mt8183_formats[] = {
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{
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.pixelformat = V4L2_PIX_FMT_GREY,
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.mdp_color = MDP_COLOR_GREY,
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.depth = { 8 },
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.row_depth = { 8 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_RGB565X,
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.mdp_color = MDP_COLOR_BGR565,
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.depth = { 16 },
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.row_depth = { 16 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_RGB565,
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.mdp_color = MDP_COLOR_RGB565,
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.depth = { 16 },
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.row_depth = { 16 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_RGB24,
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.mdp_color = MDP_COLOR_RGB888,
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.depth = { 24 },
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.row_depth = { 24 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_BGR24,
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.mdp_color = MDP_COLOR_BGR888,
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.depth = { 24 },
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.row_depth = { 24 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_ABGR32,
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.mdp_color = MDP_COLOR_BGRA8888,
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.depth = { 32 },
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.row_depth = { 32 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_ARGB32,
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.mdp_color = MDP_COLOR_ARGB8888,
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.depth = { 32 },
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.row_depth = { 32 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_UYVY,
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.mdp_color = MDP_COLOR_UYVY,
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.depth = { 16 },
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.row_depth = { 16 },
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.num_planes = 1,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_VYUY,
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.mdp_color = MDP_COLOR_VYUY,
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.depth = { 16 },
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.row_depth = { 16 },
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.num_planes = 1,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_YUYV,
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.mdp_color = MDP_COLOR_YUYV,
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.depth = { 16 },
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.row_depth = { 16 },
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.num_planes = 1,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_YVYU,
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.mdp_color = MDP_COLOR_YVYU,
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.depth = { 16 },
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.row_depth = { 16 },
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.num_planes = 1,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_YUV420,
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.mdp_color = MDP_COLOR_I420,
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.depth = { 12 },
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.row_depth = { 8 },
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.num_planes = 1,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_YVU420,
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.mdp_color = MDP_COLOR_YV12,
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.depth = { 12 },
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.row_depth = { 8 },
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.num_planes = 1,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV12,
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.mdp_color = MDP_COLOR_NV12,
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.depth = { 12 },
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.row_depth = { 8 },
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.num_planes = 1,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV21,
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.mdp_color = MDP_COLOR_NV21,
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.depth = { 12 },
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.row_depth = { 8 },
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.num_planes = 1,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV16,
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.mdp_color = MDP_COLOR_NV16,
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.depth = { 16 },
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.row_depth = { 8 },
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.num_planes = 1,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV61,
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.mdp_color = MDP_COLOR_NV61,
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.depth = { 16 },
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.row_depth = { 8 },
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.num_planes = 1,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV24,
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.mdp_color = MDP_COLOR_NV24,
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.depth = { 24 },
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.row_depth = { 8 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV42,
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.mdp_color = MDP_COLOR_NV42,
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.depth = { 24 },
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.row_depth = { 8 },
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.num_planes = 1,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_MT21C,
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.mdp_color = MDP_COLOR_420_BLK_UFO,
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.depth = { 8, 4 },
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.row_depth = { 8, 8 },
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.num_planes = 2,
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.walign = 4,
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.halign = 5,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_MM21,
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.mdp_color = MDP_COLOR_420_BLK,
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.depth = { 8, 4 },
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.row_depth = { 8, 8 },
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.num_planes = 2,
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.walign = 4,
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.halign = 5,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV12M,
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.mdp_color = MDP_COLOR_NV12,
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.depth = { 8, 4 },
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.row_depth = { 8, 8 },
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.num_planes = 2,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV21M,
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.mdp_color = MDP_COLOR_NV21,
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.depth = { 8, 4 },
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.row_depth = { 8, 8 },
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.num_planes = 2,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV16M,
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.mdp_color = MDP_COLOR_NV16,
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.depth = { 8, 8 },
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.row_depth = { 8, 8 },
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.num_planes = 2,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_NV61M,
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.mdp_color = MDP_COLOR_NV61,
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.depth = { 8, 8 },
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.row_depth = { 8, 8 },
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.num_planes = 2,
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.walign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT,
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}, {
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.pixelformat = V4L2_PIX_FMT_YUV420M,
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.mdp_color = MDP_COLOR_I420,
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.depth = { 8, 2, 2 },
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.row_depth = { 8, 4, 4 },
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.num_planes = 3,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}, {
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.pixelformat = V4L2_PIX_FMT_YVU420M,
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.mdp_color = MDP_COLOR_YV12,
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.depth = { 8, 2, 2 },
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.row_depth = { 8, 4, 4 },
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.num_planes = 3,
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.walign = 1,
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.halign = 1,
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.flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
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}
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};
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static const struct mdp_limit mt8183_mdp_def_limit = {
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.out_limit = {
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.wmin = 16,
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.hmin = 16,
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.wmax = 8176,
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.hmax = 8176,
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},
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.cap_limit = {
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.wmin = 2,
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.hmin = 2,
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.wmax = 8176,
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.hmax = 8176,
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},
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.h_scale_up_max = 32,
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.v_scale_up_max = 32,
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.h_scale_down_max = 20,
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.v_scale_down_max = 128,
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};
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static const struct mdp_pipe_info mt8183_pipe_info[] = {
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[MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0},
|
|
[MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 1},
|
|
[MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 2},
|
|
[MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 3}
|
|
};
|
|
|
|
const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
|
|
.mdp_probe_infra = mt8183_mdp_probe_infra,
|
|
.mdp_cfg = &mt8183_plat_cfg,
|
|
.mdp_mutex_table_idx = mt8183_mutex_idx,
|
|
.comp_data = mt8183_mdp_comp_data,
|
|
.comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data),
|
|
.mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids,
|
|
.format = mt8183_formats,
|
|
.format_len = ARRAY_SIZE(mt8183_formats),
|
|
.def_limit = &mt8183_mdp_def_limit,
|
|
.pipe_info = mt8183_pipe_info,
|
|
.pipe_info_len = ARRAY_SIZE(mt8183_pipe_info),
|
|
};
|
|
|
|
s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
|
|
{
|
|
if (!mdp_dev)
|
|
return MDP_COMP_NONE;
|
|
if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT)
|
|
return MDP_COMP_NONE;
|
|
|
|
return mdp_dev->mdp_data->comp_data[id].match.inner_id;
|
|
}
|
|
|
|
enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 inner_id)
|
|
{
|
|
enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
|
|
u32 i;
|
|
|
|
if (IS_ERR(mdp_dev) || !inner_id)
|
|
goto err_public_id;
|
|
|
|
for (i = 0; i < MDP_MAX_COMP_COUNT; i++) {
|
|
if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) {
|
|
public_id = i;
|
|
return public_id;
|
|
}
|
|
}
|
|
|
|
err_public_id:
|
|
return public_id;
|
|
}
|