mirror of
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8f447694c2
Pull devicetree updates from Rob Herring:
"DT core:
- Add support for generating DT nodes for PCI devices. This is the
groundwork for applying overlays to PCI devices containing
non-discoverable downstream devices.
- DT unittest additions to check reverted changesets, to test for
refcount issues, and to test unresolved symbols. Also, various
clean-ups of the unittest along the way.
- Refactor node and property manipulation functions to better share
code with old API and changeset API
- Refactor changeset print functions to a common implementation
- Move some platform_device specific functions into of_platform.c
Bindings:
- Treewide fixing of typos
- Treewide clean-up of SPDX tags to use 'OR' consistently
- Last chunk of dropping unnecessary quotes. With that, the check for
unnecessary quotes is enabled in yamllint.
- Convert ftgmac100, zynqmp-genpd, pps-gpio, syna,rmi4, and qcom,ssbi
bindings to DT schema format
- Add Allwinner V3s xHCI USB, Saef SF-TC154B display, QCom SM8450
Inline Crypto Engine, QCom SM6115 UFS, QCom SDM670 PDC interrupt
controller, Arm 2022 Cortex cores, and QCom IPQ9574 Crypto bindings
- Fixes for Rockchip DWC PCI binding
- Ensure all properties are evaluated on USB connector schema
- Fix dt-check-compatible script to find of_device_id instances with
compiler annotations"
* tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits)
dt-bindings: usb: Add V3s compatible string for OHCI
dt-bindings: usb: Add V3s compatible string for EHCI
dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
dt-bindings: vendor-prefixes: document Saef Technology
dt-bindings: thermal: lmh: update maintainer address
of: unittest: Fix of_unittest_pci_node() kconfig dependencies
dt-bindings: crypto: ice: Document sm8450 inline crypto engine
dt-bindings: ufs: qcom: Add ICE to sm8450 example
dt-bindings: ufs: qcom: Add sm6115 binding
dt-bindings: ufs: qcom: Add reg-names property for ICE
dt-bindings: yamllint: Enable quoted string check
dt-bindings: Drop remaining unneeded quotes
of: unittest-data: Fix whitespace - angular brackets
of: unittest-data: Fix whitespace - indentation
of: unittest-data: Fix whitespace - blank lines
of: unittest-data: Convert remaining overlay DTS files to sugar syntax
of: overlay: unittest: Add test for unresolved symbol
of: unittest: Add separators to of_unittest_overlay_high_level()
of: unittest: Cleanup partially-applied overlays
of: unittest: Merge of_unittest_apply{,_revert}_overlay_check()
...
144 lines
3.0 KiB
YAML
144 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare APB GPIO controller
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description: |
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Synopsys DesignWare GPIO controllers have a configurable number of ports,
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each of which are intended to be represented as child nodes with the generic
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GPIO-controller properties as described in this bindings file.
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maintainers:
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- Hoan Tran <hoan@os.amperecomputing.com>
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- Serge Semin <fancer.lancer@gmail.com>
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properties:
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$nodename:
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pattern: "^gpio@[0-9a-f]+$"
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compatible:
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const: snps,dw-apb-gpio
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: APB interface clock source
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- description: DW GPIO debounce reference clock source
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clock-names:
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minItems: 1
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items:
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- const: bus
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- const: db
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resets:
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maxItems: 1
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patternProperties:
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"^gpio-(port|controller)@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: snps,dw-apb-gpio-port
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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gpio-line-names:
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minItems: 1
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maxItems: 32
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ngpios:
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default: 32
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minimum: 1
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maximum: 32
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snps,nr-gpios:
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description: The number of GPIO pins exported by the port.
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 32
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minimum: 1
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maximum: 32
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interrupts:
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description: |
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The interrupts to the parent controller raised when GPIOs generate
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the interrupts. If the controller provides one combined interrupt
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for all GPIOs, specify a single interrupt. If the controller provides
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one interrupt for each GPIO, provide a list of interrupts that
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correspond to each of the GPIO pins.
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minItems: 1
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maxItems: 32
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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dependencies:
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interrupt-controller: [ interrupts ]
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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gpio: gpio@20000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&vic1>;
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interrupts = <0>;
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};
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portb: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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};
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};
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...
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