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Just as unevaluatedProperties or additionalProperties are required at the top level of schemas, they should (and will) also be required for child node schemas. That ensures only documented properties are present for any node. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230925212803.1976803-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
281 lines
8.7 KiB
YAML
281 lines
8.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/samsung,fimc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung S5P/Exynos SoC Camera Subsystem (FIMC)
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maintainers:
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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description: |
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The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
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represented by separate device tree nodes. Currently this includes: Fully
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Integrated Mobile Camera (FIMC, in the S5P SoCs series known as CAMIF), MIPI
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CSIS, FIMC-LITE and FIMC-IS (ISP).
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properties:
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compatible:
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const: samsung,fimc
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ranges: true
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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'#clock-cells':
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const: 1
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description: |
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The clock specifier cell stores an index of a clock: 0, 1 for
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CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively.
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clocks:
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minItems: 2
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maxItems: 4
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clock-names:
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minItems: 2
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items:
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- const: sclk_cam0
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- const: sclk_cam1
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- const: pxl_async0
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- const: pxl_async1
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clock-output-names:
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maxItems: 2
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parallel-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Active parallel video input ports.
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patternProperties:
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"^port@[01]$":
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Camera A and camera B inputs.
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: idle
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- const: active_a
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- const: active_b
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patternProperties:
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"^csis@[0-9a-f]+$":
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type: object
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$ref: samsung,exynos4210-csis.yaml#
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description: MIPI CSI-2 receiver.
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"^fimc@[0-9a-f]+$":
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type: object
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$ref: samsung,exynos4210-fimc.yaml#
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description: Fully Integrated Mobile Camera.
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"^fimc-is@[0-9a-f]+$":
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type: object
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$ref: samsung,exynos4212-fimc-is.yaml#
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description: Imaging Subsystem (FIMC-IS).
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"^fimc-lite@[0-9a-f]+$":
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type: object
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$ref: samsung,exynos4212-fimc-lite.yaml#
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description: Camera host interface (FIMC-LITE).
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required:
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- compatible
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- '#address-cells'
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- '#clock-cells'
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- clocks
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- clock-names
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- clock-output-names
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- ranges
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- '#size-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos4.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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camera@11800000 {
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compatible = "samsung,fimc";
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x18000000>;
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clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
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<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
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clock-output-names = "cam_a_clkout", "cam_b_clkout";
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assigned-clocks = <&clock CLK_MOUT_CAM0>,
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<&clock CLK_MOUT_CAM1>;
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assigned-clock-parents = <&clock CLK_XUSBXTI>,
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<&clock CLK_XUSBXTI>;
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pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
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pinctrl-names = "default";
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fimc@11800000 {
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compatible = "samsung,exynos4212-fimc";
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reg = <0x11800000 0x1000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_FIMC0>,
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<&clock CLK_SCLK_FIMC0>;
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clock-names = "fimc", "sclk_fimc";
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power-domains = <&pd_cam>;
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samsung,sysreg = <&sys_reg>;
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iommus = <&sysmmu_fimc0>;
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,isp-wb;
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samsung,cam-if;
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};
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/* ... FIMC 1-3 */
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csis@11880000 {
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compatible = "samsung,exynos4210-csis";
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reg = <0x11880000 0x4000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_CSIS0>,
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<&clock CLK_SCLK_CSIS0>;
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clock-names = "csis", "sclk_csis";
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assigned-clocks = <&clock CLK_MOUT_CSIS0>,
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<&clock CLK_SCLK_CSIS0>;
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assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
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assigned-clock-rates = <0>, <176000000>;
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bus-width = <4>;
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power-domains = <&pd_cam>;
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phys = <&mipi_phy 0>;
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phy-names = "csis";
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#address-cells = <1>;
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#size-cells = <0>;
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vddcore-supply = <&ldo8_reg>;
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vddio-supply = <&ldo10_reg>;
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/* Camera C (3) MIPI CSI-2 (CSIS0) */
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port@3 {
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reg = <3>;
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endpoint {
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remote-endpoint = <&s5c73m3_ep>;
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data-lanes = <1 2 3 4>;
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samsung,csis-hs-settle = <12>;
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};
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};
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};
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/* ... CSIS 1 */
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fimc-lite@12390000 {
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compatible = "samsung,exynos4212-fimc-lite";
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reg = <0x12390000 0x1000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_isp>;
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clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
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clock-names = "flite";
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iommus = <&sysmmu_fimc_lite0>;
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};
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/* ... FIMC-LITE 1 */
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fimc-is@12000000 {
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compatible = "samsung,exynos4212-fimc-is";
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reg = <0x12000000 0x260000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
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<&isp_clock CLK_ISP_FIMC_LITE1>,
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<&isp_clock CLK_ISP_PPMUISPX>,
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<&isp_clock CLK_ISP_PPMUISPMX>,
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<&isp_clock CLK_ISP_FIMC_ISP>,
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<&isp_clock CLK_ISP_FIMC_DRC>,
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<&isp_clock CLK_ISP_FIMC_FD>,
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<&isp_clock CLK_ISP_MCUISP>,
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<&isp_clock CLK_ISP_GICISP>,
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<&isp_clock CLK_ISP_MCUCTL_ISP>,
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<&isp_clock CLK_ISP_PWM_ISP>,
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<&isp_clock CLK_ISP_DIV_ISP0>,
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<&isp_clock CLK_ISP_DIV_ISP1>,
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<&isp_clock CLK_ISP_DIV_MCUISP0>,
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<&isp_clock CLK_ISP_DIV_MCUISP1>,
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<&clock CLK_MOUT_MPLL_USER_T>,
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<&clock CLK_ACLK200>,
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<&clock CLK_ACLK400_MCUISP>,
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<&clock CLK_DIV_ACLK200>,
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<&clock CLK_DIV_ACLK400_MCUISP>,
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<&clock CLK_UART_ISP_SCLK>;
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clock-names = "lite0", "lite1", "ppmuispx",
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"ppmuispmx", "isp",
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"drc", "fd", "mcuisp",
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"gicisp", "mcuctl_isp", "pwm_isp",
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"ispdiv0", "ispdiv1", "mcuispdiv0",
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"mcuispdiv1", "mpll", "aclk200",
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"aclk400mcuisp", "div_aclk200",
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"div_aclk400mcuisp", "uart";
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iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
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<&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
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iommu-names = "isp", "drc", "fd", "mcuctl";
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power-domains = <&pd_isp>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pmu@10020000 {
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reg = <0x10020000 0x3000>;
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};
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i2c-isp@12140000 {
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compatible = "samsung,exynos4212-i2c-isp";
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reg = <0x12140000 0x100>;
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clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
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clock-names = "i2c_isp";
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pinctrl-0 = <&fimc_is_i2c1>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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image-sensor@10 {
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compatible = "samsung,s5k6a3";
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reg = <0x10>;
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svdda-supply = <&cam_io_reg>;
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svddio-supply = <&ldo19_reg>;
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afvdd-supply = <&ldo19_reg>;
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clock-frequency = <24000000>;
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/* CAM_B_CLKOUT */
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clocks = <&camera 1>;
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clock-names = "extclk";
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gpios = <&gpm1 6 GPIO_ACTIVE_LOW>;
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port {
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endpoint {
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remote-endpoint = <&csis1_ep>;
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data-lanes = <1>;
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};
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};
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};
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};
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};
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};
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